Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave dmaengine fixes from Vinod Koul: "Four fixes for dw, pl08x, imx-sdma and at_hdmac driver. Nothing unusual here, simple fixes to these drivers" * 'fixes' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: pl08x: Define capabilities for generic capabilities reporting dmaengine: dw: append MODULE_ALIAS for platform driver dmaengine: imx-sdma: switch to dynamic context mode after script loaded dmaengine: at_hdmac: Fix calculation of the residual bytes
This commit is contained in:
commit
f897522468
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@ -97,6 +97,12 @@
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#define DRIVER_NAME "pl08xdmac"
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#define PL80X_DMA_BUSWIDTHS \
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BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
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BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
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static struct amba_driver pl08x_amba_driver;
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struct pl08x_driver_data;
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@ -2070,6 +2076,10 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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pl08x->memcpy.device_pause = pl08x_pause;
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pl08x->memcpy.device_resume = pl08x_resume;
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pl08x->memcpy.device_terminate_all = pl08x_terminate_all;
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pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS;
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pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
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pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM);
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pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
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/* Initialize slave engine */
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dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
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@ -2086,6 +2096,10 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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pl08x->slave.device_pause = pl08x_pause;
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pl08x->slave.device_resume = pl08x_resume;
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pl08x->slave.device_terminate_all = pl08x_terminate_all;
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pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS;
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pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
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pl08x->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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pl08x->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
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/* Get the platform data */
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pl08x->pd = dev_get_platdata(&adev->dev);
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@ -238,93 +238,126 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
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}
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/*
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* atc_get_current_descriptors -
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* locate the descriptor which equal to physical address in DSCR
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* @atchan: the channel we want to start
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* @dscr_addr: physical descriptor address in DSCR
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* atc_get_desc_by_cookie - get the descriptor of a cookie
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* @atchan: the DMA channel
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* @cookie: the cookie to get the descriptor for
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*/
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static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan,
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u32 dscr_addr)
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static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan,
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dma_cookie_t cookie)
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{
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struct at_desc *desc, *_desc, *child, *desc_cur = NULL;
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struct at_desc *desc, *_desc;
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list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) {
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if (desc->txd.cookie == cookie)
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return desc;
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}
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list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
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if (desc->lli.dscr == dscr_addr) {
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desc_cur = desc;
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break;
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}
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list_for_each_entry(child, &desc->tx_list, desc_node) {
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if (child->lli.dscr == dscr_addr) {
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desc_cur = child;
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break;
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}
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}
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if (desc->txd.cookie == cookie)
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return desc;
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}
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return desc_cur;
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return NULL;
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}
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/*
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* atc_get_bytes_left -
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* Get the number of bytes residue in dma buffer,
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* @chan: the channel we want to start
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/**
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* atc_calc_bytes_left - calculates the number of bytes left according to the
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* value read from CTRLA.
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*
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* @current_len: the number of bytes left before reading CTRLA
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* @ctrla: the value of CTRLA
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* @desc: the descriptor containing the transfer width
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*/
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static int atc_get_bytes_left(struct dma_chan *chan)
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static inline int atc_calc_bytes_left(int current_len, u32 ctrla,
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struct at_desc *desc)
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{
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return current_len - ((ctrla & ATC_BTSIZE_MAX) << desc->tx_width);
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}
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/**
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* atc_calc_bytes_left_from_reg - calculates the number of bytes left according
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* to the current value of CTRLA.
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*
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* @current_len: the number of bytes left before reading CTRLA
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* @atchan: the channel to read CTRLA for
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* @desc: the descriptor containing the transfer width
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*/
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static inline int atc_calc_bytes_left_from_reg(int current_len,
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struct at_dma_chan *atchan, struct at_desc *desc)
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{
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u32 ctrla = channel_readl(atchan, CTRLA);
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return atc_calc_bytes_left(current_len, ctrla, desc);
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}
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/**
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* atc_get_bytes_left - get the number of bytes residue for a cookie
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* @chan: DMA channel
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* @cookie: transaction identifier to check status of
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*/
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static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)
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{
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struct at_dma_chan *atchan = to_at_dma_chan(chan);
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struct at_dma *atdma = to_at_dma(chan->device);
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int chan_id = atchan->chan_common.chan_id;
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struct at_desc *desc_first = atc_first_active(atchan);
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struct at_desc *desc_cur;
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int ret = 0, count = 0;
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struct at_desc *desc;
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int ret;
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u32 ctrla, dscr;
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/*
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* Initialize necessary values in the first time.
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* remain_desc record remain desc length.
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* If the cookie doesn't match to the currently running transfer then
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* we can return the total length of the associated DMA transfer,
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* because it is still queued.
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*/
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if (atchan->remain_desc == 0)
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/* First descriptor embedds the transaction length */
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atchan->remain_desc = desc_first->len;
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desc = atc_get_desc_by_cookie(atchan, cookie);
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if (desc == NULL)
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return -EINVAL;
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else if (desc != desc_first)
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return desc->total_len;
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/*
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* This happens when current descriptor transfer complete.
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* The residual buffer size should reduce current descriptor length.
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*/
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if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) {
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clear_bit(ATC_IS_BTC, &atchan->status);
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desc_cur = atc_get_current_descriptors(atchan,
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channel_readl(atchan, DSCR));
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if (!desc_cur) {
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ret = -EINVAL;
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goto out;
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}
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/* cookie matches to the currently running transfer */
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ret = desc_first->total_len;
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count = (desc_cur->lli.ctrla & ATC_BTSIZE_MAX)
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<< desc_first->tx_width;
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if (atchan->remain_desc < count) {
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ret = -EINVAL;
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goto out;
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}
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if (desc_first->lli.dscr) {
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/* hardware linked list transfer */
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atchan->remain_desc -= count;
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ret = atchan->remain_desc;
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} else {
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/*
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* Get residual bytes when current
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* descriptor transfer in progress.
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* Calculate the residue by removing the length of the child
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* descriptors already transferred from the total length.
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* To get the current child descriptor we can use the value of
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* the channel's DSCR register and compare it against the value
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* of the hardware linked list structure of each child
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* descriptor.
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*/
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count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX)
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<< (desc_first->tx_width);
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ret = atchan->remain_desc - count;
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}
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/*
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* Check fifo empty.
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*/
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if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id)))
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atc_issue_pending(chan);
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out:
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ctrla = channel_readl(atchan, CTRLA);
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rmb(); /* ensure CTRLA is read before DSCR */
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dscr = channel_readl(atchan, DSCR);
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/* for the first descriptor we can be more accurate */
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if (desc_first->lli.dscr == dscr)
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return atc_calc_bytes_left(ret, ctrla, desc_first);
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ret -= desc_first->len;
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list_for_each_entry(desc, &desc_first->tx_list, desc_node) {
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if (desc->lli.dscr == dscr)
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break;
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ret -= desc->len;
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}
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/*
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* For the last descriptor in the chain we can calculate
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* the remaining bytes using the channel's register.
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* Note that the transfer width of the first and last
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* descriptor may differ.
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*/
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if (!desc->lli.dscr)
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ret = atc_calc_bytes_left_from_reg(ret, atchan, desc);
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} else {
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/* single transfer */
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ret = atc_calc_bytes_left_from_reg(ret, atchan, desc_first);
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}
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return ret;
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}
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@ -539,8 +572,6 @@ static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
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/* Give information to tasklet */
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set_bit(ATC_IS_ERROR, &atchan->status);
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}
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if (pending & AT_DMA_BTC(i))
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set_bit(ATC_IS_BTC, &atchan->status);
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tasklet_schedule(&atchan->tasklet);
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ret = IRQ_HANDLED;
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}
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@ -653,14 +684,18 @@ atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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desc->lli.ctrlb = ctrlb;
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desc->txd.cookie = 0;
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desc->len = xfer_count << src_width;
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atc_desc_chain(&first, &prev, desc);
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}
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->len = len;
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first->total_len = len;
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/* set transfer width for the calculation of the residue */
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first->tx_width = src_width;
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prev->tx_width = src_width;
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/* set end-of-link to the last link descriptor of list*/
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set_desc_eol(desc);
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|
@ -752,6 +787,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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| ATC_SRC_WIDTH(mem_width)
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| len >> mem_width;
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desc->lli.ctrlb = ctrlb;
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desc->len = len;
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atc_desc_chain(&first, &prev, desc);
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total_len += len;
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@ -792,6 +828,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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| ATC_DST_WIDTH(mem_width)
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| len >> reg_width;
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desc->lli.ctrlb = ctrlb;
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desc->len = len;
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atc_desc_chain(&first, &prev, desc);
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total_len += len;
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|
@ -806,8 +843,11 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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/* First descriptor of the chain embedds additional information */
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first->txd.cookie = -EBUSY;
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first->len = total_len;
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first->total_len = total_len;
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/* set transfer width for the calculation of the residue */
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first->tx_width = reg_width;
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prev->tx_width = reg_width;
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/* first link descriptor of list is responsible of flags */
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first->txd.flags = flags; /* client is in control of this ack */
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|
@ -872,6 +912,7 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
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| ATC_FC_MEM2PER
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| ATC_SIF(atchan->mem_if)
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| ATC_DIF(atchan->per_if);
|
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desc->len = period_len;
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break;
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|
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case DMA_DEV_TO_MEM:
|
||||
|
@ -883,6 +924,7 @@ atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
|
|||
| ATC_FC_PER2MEM
|
||||
| ATC_SIF(atchan->per_if)
|
||||
| ATC_DIF(atchan->mem_if);
|
||||
desc->len = period_len;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -964,7 +1006,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
|||
|
||||
/* First descriptor of the chain embedds additional information */
|
||||
first->txd.cookie = -EBUSY;
|
||||
first->len = buf_len;
|
||||
first->total_len = buf_len;
|
||||
first->tx_width = reg_width;
|
||||
|
||||
return &first->txd;
|
||||
|
@ -1118,7 +1160,7 @@ atc_tx_status(struct dma_chan *chan,
|
|||
spin_lock_irqsave(&atchan->lock, flags);
|
||||
|
||||
/* Get number of bytes left in the active transactions */
|
||||
bytes = atc_get_bytes_left(chan);
|
||||
bytes = atc_get_bytes_left(chan, cookie);
|
||||
|
||||
spin_unlock_irqrestore(&atchan->lock, flags);
|
||||
|
||||
|
@ -1214,7 +1256,6 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
|
|||
|
||||
spin_lock_irqsave(&atchan->lock, flags);
|
||||
atchan->descs_allocated = i;
|
||||
atchan->remain_desc = 0;
|
||||
list_splice(&tmp_list, &atchan->free_list);
|
||||
dma_cookie_init(chan);
|
||||
spin_unlock_irqrestore(&atchan->lock, flags);
|
||||
|
@ -1257,7 +1298,6 @@ static void atc_free_chan_resources(struct dma_chan *chan)
|
|||
list_splice_init(&atchan->free_list, &list);
|
||||
atchan->descs_allocated = 0;
|
||||
atchan->status = 0;
|
||||
atchan->remain_desc = 0;
|
||||
|
||||
dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
|
||||
}
|
||||
|
|
|
@ -181,8 +181,9 @@ struct at_lli {
|
|||
* @at_lli: hardware lli structure
|
||||
* @txd: support for the async_tx api
|
||||
* @desc_node: node on the channed descriptors list
|
||||
* @len: total transaction bytecount
|
||||
* @len: descriptor byte count
|
||||
* @tx_width: transfer width
|
||||
* @total_len: total transaction byte count
|
||||
*/
|
||||
struct at_desc {
|
||||
/* FIRST values the hardware uses */
|
||||
|
@ -194,6 +195,7 @@ struct at_desc {
|
|||
struct list_head desc_node;
|
||||
size_t len;
|
||||
u32 tx_width;
|
||||
size_t total_len;
|
||||
};
|
||||
|
||||
static inline struct at_desc *
|
||||
|
@ -213,7 +215,6 @@ txd_to_at_desc(struct dma_async_tx_descriptor *txd)
|
|||
enum atc_status {
|
||||
ATC_IS_ERROR = 0,
|
||||
ATC_IS_PAUSED = 1,
|
||||
ATC_IS_BTC = 2,
|
||||
ATC_IS_CYCLIC = 24,
|
||||
};
|
||||
|
||||
|
@ -231,7 +232,6 @@ enum atc_status {
|
|||
* @save_cfg: configuration register that is saved on suspend/resume cycle
|
||||
* @save_dscr: for cyclic operations, preserve next descriptor address in
|
||||
* the cyclic list on suspend/resume cycle
|
||||
* @remain_desc: to save remain desc length
|
||||
* @dma_sconfig: configuration for slave transfers, passed via
|
||||
* .device_config
|
||||
* @lock: serializes enqueue/dequeue operations to descriptors lists
|
||||
|
@ -251,7 +251,6 @@ struct at_dma_chan {
|
|||
struct tasklet_struct tasklet;
|
||||
u32 save_cfg;
|
||||
u32 save_dscr;
|
||||
u32 remain_desc;
|
||||
struct dma_slave_config dma_sconfig;
|
||||
|
||||
spinlock_t lock;
|
||||
|
|
|
@ -26,6 +26,8 @@
|
|||
|
||||
#include "internal.h"
|
||||
|
||||
#define DRV_NAME "dw_dmac"
|
||||
|
||||
static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
|
@ -284,7 +286,7 @@ static struct platform_driver dw_driver = {
|
|||
.remove = dw_remove,
|
||||
.shutdown = dw_shutdown,
|
||||
.driver = {
|
||||
.name = "dw_dmac",
|
||||
.name = DRV_NAME,
|
||||
.pm = &dw_dev_pm_ops,
|
||||
.of_match_table = of_match_ptr(dw_dma_of_id_table),
|
||||
.acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
|
||||
|
@ -305,3 +307,4 @@ module_exit(dw_exit);
|
|||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
|
|
|
@ -531,6 +531,10 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
|
|||
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
|
||||
}
|
||||
|
||||
/* Set bits of CONFIG register with dynamic context switching */
|
||||
if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
|
||||
writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
|
||||
|
||||
return ret ? 0 : -ETIMEDOUT;
|
||||
}
|
||||
|
||||
|
@ -1394,9 +1398,6 @@ static int sdma_init(struct sdma_engine *sdma)
|
|||
|
||||
writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
|
||||
|
||||
/* Set bits of CONFIG register with given context switching mode */
|
||||
writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
|
||||
|
||||
/* Initializes channel's priorities */
|
||||
sdma_set_channel_priority(&sdma->channel[0], 7);
|
||||
|
||||
|
|
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Reference in a new issue