mmc: sh_mmcif: double clock speed
Correct an off-by one error when calculating the clock divisor in cases where the host clock is a power of two of the target clock. Previously the divisor was one greater than the correct value in these cases leading to the clock being set at half the desired speed. Thanks to Guennadi Liakhovetski for working with me on the logic for this change. Tested-by: Cao Minh Hiep <hiepcm@gmail.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -454,7 +454,8 @@ static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
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else
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
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((fls(host->clk / clk) - 1) << 16));
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((fls(DIV_ROUND_UP(host->clk,
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clk) - 1) - 1) << 16));
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
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}
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