arm64: assembler: Change order of macro arguments in phys_to_ttbr
Since AArch64 assembly instructions take the destination register as their first operand, do the same thing for the phys_to_ttbr macro. Acked-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -514,7 +514,7 @@ alternative_endif
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* phys: physical address, preserved
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* ttbr: returns the TTBR value
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*/
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.macro phys_to_ttbr, phys, ttbr
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.macro phys_to_ttbr, ttbr, phys
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#ifdef CONFIG_ARM64_PA_BITS_52
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orr \ttbr, \phys, \phys, lsr #46
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and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
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@ -776,8 +776,8 @@ ENTRY(__enable_mmu)
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update_early_cpu_boot_status 0, x1, x2
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adrp x1, idmap_pg_dir
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adrp x2, swapper_pg_dir
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phys_to_ttbr x1, x3
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phys_to_ttbr x2, x4
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phys_to_ttbr x3, x1
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phys_to_ttbr x4, x2
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msr ttbr0_el1, x3 // load TTBR0
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msr ttbr1_el1, x4 // load TTBR1
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isb
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@ -34,12 +34,12 @@
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* each stage of the walk.
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*/
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.macro break_before_make_ttbr_switch zero_page, page_table, tmp
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phys_to_ttbr \zero_page, \tmp
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phys_to_ttbr \tmp, \zero_page
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msr ttbr1_el1, \tmp
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isb
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tlbi vmalle1
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dsb nsh
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phys_to_ttbr \page_table, \tmp
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phys_to_ttbr \tmp, \page_table
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msr ttbr1_el1, \tmp
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isb
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.endm
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@ -63,7 +63,7 @@ __do_hyp_init:
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cmp x0, #HVC_STUB_HCALL_NR
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b.lo __kvm_handle_stub_hvc
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phys_to_ttbr x0, x4
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phys_to_ttbr x4, x0
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msr ttbr0_el2, x4
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mrs x4, tcr_el1
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@ -153,7 +153,7 @@ ENDPROC(cpu_do_resume)
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ENTRY(cpu_do_switch_mm)
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mrs x2, ttbr1_el1
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mmid x1, x1 // get mm->context.id
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phys_to_ttbr x0, x3
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phys_to_ttbr x3, x0
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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bfi x3, x1, #48, #16 // set the ASID field in TTBR0
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#endif
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@ -169,7 +169,7 @@ ENDPROC(cpu_do_switch_mm)
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.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
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adrp \tmp1, empty_zero_page
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phys_to_ttbr \tmp1, \tmp2
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phys_to_ttbr \tmp2, \tmp1
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msr ttbr1_el1, \tmp2
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isb
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tlbi vmalle1
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@ -188,7 +188,7 @@ ENTRY(idmap_cpu_replace_ttbr1)
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__idmap_cpu_set_reserved_ttbr1 x1, x3
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phys_to_ttbr x0, x3
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phys_to_ttbr x3, x0
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msr ttbr1_el1, x3
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isb
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