MLK-17491-21 clk: imx7ulp: fix RTC OSC clock name
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
pull/10/head
Dong Aisheng
Jason Liu
parent
9dc495b3f7
commit
fc24da6cdb
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@ -25,8 +25,8 @@
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clks_m4: scg0@41027000 {
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compatible = "fsl,imx7ulp-scg0";
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reg = <0x41027000 0x1000>;
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clocks = <&cm4_ckil>, <&cm4_osc>, <&cm4_sirc>, <&cm4_firc>;
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clock-names = "cm4_ckil", "cm4_osc", "cm4_sirc", "cm4_firc";
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clocks = <&cm4_rosc>, <&cm4_sosc>, <&cm4_sirc>, <&cm4_firc>;
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clock-names = "cm4_rosc", "cm4_sosc", "cm4_sirc", "cm4_firc";
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#clock-cells = <1>;
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};
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@ -83,18 +83,18 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cm4_ckil: clock@6 {
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cm4_rosc: clock@6 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "cm4_ckil";
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clock-output-names = "cm4_rosc";
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};
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cm4_osc: clock@7 {
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cm4_sosc: clock@7 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "cm4_osc";
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clock-output-names = "cm4_sosc";
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};
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cm4_sirc: clock@8 {
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@ -201,7 +201,7 @@
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<&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1>,
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<&clks_m4 IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2>,
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<&clks_m4 IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV>;
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assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_OSC>;
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assigned-clock-parents = <&clks_m4 IMX7ULP_CM4_CLK_SOSC>;
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assigned-clock-rates = <0>, <540672000>, <49152000>, <12288000>, <270336000>;
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};
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@ -94,18 +94,18 @@
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#address-cells = <1>;
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#size-cells = <0>;
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ckil: clock@0 {
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rosc: clock@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ckil";
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clock-output-names = "rosc";
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};
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osc: clock@1 {
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sosc: clock@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc";
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clock-output-names = "sosc";
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};
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sirc: clock@2 {
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@ -202,7 +202,7 @@
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reg = <0x40250000 0x1000>;
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nxp,pwm-number = <6>;
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assigned-clocks = <&clks IMX7ULP_CLK_LPTPM4>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>;
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clocks = <&clks IMX7ULP_CLK_LPTPM4>;
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#pwm-cells = <2>;
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};
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@ -283,7 +283,7 @@
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clocks = <&clks IMX7ULP_CLK_LPUART4>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>;
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assigned-clock-rates = <24000000>;
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status = "disabled";
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};
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@ -388,14 +388,14 @@
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clks: scg1@403E0000 {
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compatible = "fsl,imx7ulp-scg1";
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reg = <0x403E0000 0x10000>;
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clocks = <&ckil>, <&osc>, <&sirc>,
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clocks = <&rosc>, <&sosc>, <&sirc>,
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<&firc>, <&upll>, <&mpll>;
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clock-names = "ckil", "osc", "sirc",
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clock-names = "rosc", "sosc", "sirc",
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"firc", "upll", "mpll";
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#clock-cells = <1>;
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assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
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<&clks IMX7ULP_CLK_USDHC1>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
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assigned-clock-parents = <&clks IMX7ULP_CLK_SOSC>,
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<&clks IMX7ULP_CLK_NIC1_DIV>;
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};
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@ -20,29 +20,30 @@
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#include "clk.h"
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static const char *pll_pre_sels[] = { "osc", "firc", };
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static const char *pll_pre_sels[] = { "sosc", "firc", };
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static const char *spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", };
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static const char *spll_sels[] = { "spll", "spll_pfd_sel", };
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static const char *apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", };
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static const char *apll_sels[] = { "apll", "apll_pfd_sel", };
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static const char *sys_sels[] = { "dummy", "osc", "sirc", "firc", "ckil", "apll_sel", "spll_sel", "upll", };
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static const char *sys_sels[] = { "dummy", "sosc", "sirc", "firc", "rosc", "apll_sel", "spll_sel", "upll", };
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static const char *arm_sels[] = { "core_div", "dummy", "dummy", "hsrun_core", };
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static const char *ddr_sels[] = { "apll_pfd_sel", "upll", };
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static const char *nic_sels[] = { "firc", "ddr_div", };
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static const char *periph_plat_sels[] = { "dummy", "nic1_bus", "nic1_div", "ddr_div", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
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/* the dummy in only a space holder of spll_bus clk */
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static const char *periph_slow_sels[] = { "dummy", "osc", "dummy", "firc", "ckil", "nic1_bus", "nic1_div", "dummy", };
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static const char *periph_slow_sels[] = { "dummy", "sosc", "dummy", "firc", "rosc", "nic1_bus", "nic1_div", "dummy", };
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static struct clk *clks[IMX7ULP_CLK_END];
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static struct clk_onecell_data clk_data;
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static const char *cm4_pll_pre_sels[] = { "cm4_osc", "cm4_firc", };
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static const char *cm4_pll_pre_sels[] = { "cm4_sosc", "cm4_firc", };
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static const char *cm4_spll_pfd_sels[] = { "cm4_spll_pfd0", "cm4_spll_pfd1", "cm4_spll_pfd2", "cm4_spll_pfd3", };
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static const char *cm4_spll_sels[] = { "cm4_spll_vco", "cm4_spll_pfd_sel", };
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static const char *cm4_apll_pfd_sels[] = { "cm4_apll_pfd0", "cm4_apll_pfd1", "cm4_apll_pfd2", "cm4_apll_pfd3", };
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static const char *cm4_apll_sels[] = { "cm4_apll_vco_post_div2", "cm4_apll_pfd_sel", };
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static const char *cm4_sys_sels[] = { "cm4_dummy", "cm4_osc", "cm4_sirc", "cm4_firc", "cm4_ckil", "cm4_apll_sel", "cm4_spll_sel", "cm4_dummy", };
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static const char *cm4_periph_slow_sels[] = { "cm4_dummy", "cm4_osc", "cm4_sirc", "cm4_firc", "cm4_ckil", "cm4_bus_div", "cm4_spll_pfd2", "cm4_apll_pfd0_pre_div", };
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static const char *scg0_clkout_sels[] = { "dummy", "cm4_osc", "cm4_sirc", "cm4_firc", "cm4_ckil", "cm4_apll_sel", "cm4_spll_sel", "dummy"};
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static const char *cm4_sys_sels[] = { "cm4_dummy", "cm4_sosc", "cm4_sirc", "cm4_firc", "cm4_rosc", "cm4_apll_sel", "cm4_spll_sel", "cm4_dummy", };
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static const char *cm4_periph_slow_sels[] = { "cm4_dummy", "cm4_sosc", "cm4_sirc", "cm4_firc", "cm4_rosc", "cm4_bus_div", "cm4_spll_pfd2", "cm4_apll_pfd0_pre_div", };
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static const char *scg0_clkout_sels[] = { "dummy", "cm4_sosc", "cm4_sirc", "cm4_firc", "cm4_rosc", "cm4_apll_sel", "cm4_spll_sel", "dummy"};
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static struct clk *clks_cm4[IMX7ULP_CM4_CLK_END];
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static struct clk_onecell_data clk_data_cm4;
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@ -70,8 +71,8 @@ static void __init imx7ulp_clocks_init(struct device_node *scg_node)
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clks[IMX7ULP_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clks[IMX7ULP_CLK_CKIL] = of_clk_get_by_name(scg_node, "ckil");
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clks[IMX7ULP_CLK_OSC] = of_clk_get_by_name(scg_node, "osc");
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clks[IMX7ULP_CLK_ROSC] = of_clk_get_by_name(scg_node, "rosc");
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clks[IMX7ULP_CLK_SOSC] = of_clk_get_by_name(scg_node, "sosc");
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clks[IMX7ULP_CLK_SIRC] = of_clk_get_by_name(scg_node, "sirc");
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clks[IMX7ULP_CLK_FIRC] = of_clk_get_by_name(scg_node, "firc");
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clks[IMX7ULP_CLK_MIPI_PLL] = of_clk_get_by_name(scg_node, "mpll");
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@ -215,8 +216,8 @@ static void __init imx7ulp_cm4_clocks_init(struct device_node *scg_node)
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clks_cm4[IMX7ULP_CM4_CLK_DUMMY] = imx_clk_fixed("cm4_dummy", 0);
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clks_cm4[IMX7ULP_CM4_CLK_CKIL] = of_clk_get_by_name(scg_node, "cm4_ckil");
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clks_cm4[IMX7ULP_CM4_CLK_OSC] = of_clk_get_by_name(scg_node, "cm4_osc");
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clks_cm4[IMX7ULP_CM4_CLK_ROSC] = of_clk_get_by_name(scg_node, "cm4_rosc");
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clks_cm4[IMX7ULP_CM4_CLK_SOSC] = of_clk_get_by_name(scg_node, "cm4_sosc");
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clks_cm4[IMX7ULP_CM4_CLK_SIRC] = of_clk_get_by_name(scg_node, "cm4_sirc");
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clks_cm4[IMX7ULP_CM4_CLK_FIRC] = of_clk_get_by_name(scg_node, "cm4_firc");
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@ -12,8 +12,8 @@
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#define __DT_BINDINGS_CLOCK_IMX7ULP_H
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#define IMX7ULP_CLK_DUMMY 0
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#define IMX7ULP_CLK_CKIL 1
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#define IMX7ULP_CLK_OSC 2
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#define IMX7ULP_CLK_ROSC 1
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#define IMX7ULP_CLK_SOSC 2
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#define IMX7ULP_CLK_FIRC 3
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/* SCG1 */
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@ -110,8 +110,8 @@
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/*cm4 clocks*/
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#define IMX7ULP_CM4_CLK_DUMMY 0
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#define IMX7ULP_CM4_CLK_CKIL 1
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#define IMX7ULP_CM4_CLK_OSC 2
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#define IMX7ULP_CM4_CLK_ROSC 1
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#define IMX7ULP_CM4_CLK_SOSC 2
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#define IMX7ULP_CM4_CLK_FIRC 3
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#define IMX7ULP_CM4_CLK_SIRC 4
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