MIPS: BMIPS: Introduce helper function to change the reset vector
This will need to be called from a few different places, and the logic is starting to get a bit hairy (with the need for IPIs, CPU bug workarounds, and hazards). Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8158/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -35,6 +35,7 @@
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#include <asm/bmips.h>
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#include <asm/traps.h>
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#include <asm/barrier.h>
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#include <asm/cpu-features.h>
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static int __maybe_unused max_cpus = 1;
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@ -43,6 +44,9 @@ int bmips_smp_enabled = 1;
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int bmips_cpu_offset;
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cpumask_t bmips_booted_mask;
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#define RESET_FROM_KSEG0 0x80080800
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#define RESET_FROM_KSEG1 0xa0080800
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#ifdef CONFIG_SMP
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/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
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@ -463,10 +467,61 @@ static inline void bmips_nmi_handler_setup(void)
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&bmips_smp_int_vec_end);
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}
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struct reset_vec_info {
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int cpu;
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u32 val;
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};
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static void bmips_set_reset_vec_remote(void *vinfo)
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{
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struct reset_vec_info *info = vinfo;
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int shift = info->cpu & 0x01 ? 16 : 0;
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u32 mask = ~(0xffff << shift), val = info->val >> 16;
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preempt_disable();
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if (smp_processor_id() > 0) {
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smp_call_function_single(0, &bmips_set_reset_vec_remote,
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info, 1);
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} else {
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if (info->cpu & 0x02) {
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/* BMIPS5200 "should" use mask/shift, but it's buggy */
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bmips_write_zscm_reg(0xa0, (val << 16) | val);
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bmips_read_zscm_reg(0xa0);
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} else {
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write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
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(val << shift));
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}
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}
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preempt_enable();
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}
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static void bmips_set_reset_vec(int cpu, u32 val)
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{
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struct reset_vec_info info;
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if (current_cpu_type() == CPU_BMIPS5000) {
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/* this needs to run from CPU0 (which is always online) */
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info.cpu = cpu;
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info.val = val;
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bmips_set_reset_vec_remote(&info);
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} else {
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void __iomem *cbr = BMIPS_GET_CBR();
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if (cpu == 0)
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__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
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else {
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if (current_cpu_type() != CPU_BMIPS4380)
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return;
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__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
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}
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}
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__sync();
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back_to_back_c0_hazard();
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}
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void bmips_ebase_setup(void)
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{
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unsigned long new_ebase = ebase;
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void __iomem __maybe_unused *cbr;
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BUG_ON(ebase != CKSEG0);
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@ -492,9 +547,7 @@ void bmips_ebase_setup(void)
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* 0x8000_0400: normal vectors
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*/
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new_ebase = 0x80000400;
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cbr = BMIPS_GET_CBR();
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__raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
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__raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
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bmips_set_reset_vec(0, RESET_FROM_KSEG0);
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break;
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case CPU_BMIPS5000:
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/*
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@ -502,10 +555,8 @@ void bmips_ebase_setup(void)
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* 0x8000_1000: normal vectors
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*/
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new_ebase = 0x80001000;
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write_c0_brcm_bootvec(0xa0088008);
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bmips_set_reset_vec(0, RESET_FROM_KSEG0);
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write_c0_ebase(new_ebase);
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if (max_cpus > 2)
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bmips_write_zscm_reg(0xa0, 0xa008a008);
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break;
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default:
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return;
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