tg3: 5785 enhancements
This patch refines support for the 5785 device. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>wifi-calibration
Matt Carlson
David S. Miller
parent
9c61d6bc56
commit
fcb389dfd8
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@ -880,10 +880,45 @@ static int tg3_mdio_reset(struct mii_bus *bp)
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static void tg3_mdio_config_5785(struct tg3 *tp)
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{
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u32 val;
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struct phy_device *phydev;
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if (tp->mdio_bus->phy_map[PHY_ADDR]->interface !=
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PHY_INTERFACE_MODE_RGMII)
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
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case TG3_PHY_ID_BCM50610:
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val = MAC_PHYCFG2_50610_LED_MODES;
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break;
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case TG3_PHY_ID_BCMAC131:
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val = MAC_PHYCFG2_AC131_LED_MODES;
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break;
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case TG3_PHY_ID_RTL8211C:
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val = MAC_PHYCFG2_RTL8211C_LED_MODES;
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break;
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case TG3_PHY_ID_RTL8201E:
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val = MAC_PHYCFG2_RTL8201E_LED_MODES;
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break;
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default:
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return;
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}
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if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
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tw32(MAC_PHYCFG2, val);
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val = tr32(MAC_PHYCFG1);
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val &= ~MAC_PHYCFG1_RGMII_INT;
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tw32(MAC_PHYCFG1, val);
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return;
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}
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if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
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val |= MAC_PHYCFG2_EMODE_MASK_MASK |
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MAC_PHYCFG2_FMODE_MASK_MASK |
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MAC_PHYCFG2_GMODE_MASK_MASK |
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MAC_PHYCFG2_ACT_MASK_MASK |
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MAC_PHYCFG2_QUAL_MASK_MASK |
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MAC_PHYCFG2_INBAND_ENABLE;
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tw32(MAC_PHYCFG2, val);
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val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
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MAC_PHYCFG1_RGMII_SND_STAT_EN);
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@ -895,11 +930,6 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
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}
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tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
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val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
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if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
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val |= MAC_PHYCFG2_INBAND_ENABLE;
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tw32(MAC_PHYCFG2, val);
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val = tr32(MAC_EXT_RGMII_MODE);
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val &= ~(MAC_RGMII_MODE_RX_INT_B |
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MAC_RGMII_MODE_RX_QUALITY |
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@ -908,7 +938,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
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MAC_RGMII_MODE_TX_ENABLE |
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MAC_RGMII_MODE_TX_LOWPWR |
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MAC_RGMII_MODE_TX_RESET);
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
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if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
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val |= MAC_RGMII_MODE_RX_INT_B |
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MAC_RGMII_MODE_RX_QUALITY |
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@ -1005,14 +1035,17 @@ static int tg3_mdio_init(struct tg3 *tp)
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switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
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case TG3_PHY_ID_BCM50610:
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phydev->interface = PHY_INTERFACE_MODE_RGMII;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
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phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
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phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
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if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
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phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
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/* fallthru */
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case TG3_PHY_ID_RTL8211C:
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phydev->interface = PHY_INTERFACE_MODE_RGMII;
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break;
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case TG3_PHY_ID_RTL8201E:
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case TG3_PHY_ID_BCMAC131:
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phydev->interface = PHY_INTERFACE_MODE_MII;
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break;
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@ -1314,6 +1347,15 @@ static void tg3_adjust_link(struct net_device *dev)
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udelay(40);
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
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if (phydev->speed == SPEED_10)
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tw32(MAC_MI_STAT,
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MAC_MI_STAT_10MBPS_MODE |
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MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
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else
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tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
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}
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if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
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tw32(MAC_TX_LENGTHS,
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((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
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@ -5817,13 +5859,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
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pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
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if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
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pcie_set_readrq(tp->pdev, 4096);
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else {
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pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
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tp->pci_cacheline_sz);
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pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
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tp->pci_lat_timer);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
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if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
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pcie_set_readrq(tp->pdev, 4096);
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else {
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pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
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tp->pci_cacheline_sz);
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pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
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tp->pci_lat_timer);
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}
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}
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/* Make sure PCI-X relaxed ordering bit is clear. */
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@ -5980,8 +6024,9 @@ static int tg3_chip_reset(struct tg3 *tp)
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pci_write_config_dword(tp->pdev, 0xc4,
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cfg_val | (1 << 15));
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}
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/* Set PCIE max payload size and clear error status. */
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pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
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/* Set PCIE max payload size and clear error status. */
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pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
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}
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tg3_restore_pci_state(tp);
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@ -7149,8 +7194,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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return err;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
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/* This value is determined during the probe time DMA
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* engine test, tg3_test_dma.
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*/
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@ -12156,7 +12200,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
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tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
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}
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}
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
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/* If we have an AMD 762 or VIA K8T800 chipset, write
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* reordering to the mailbox registers done by the host
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@ -417,6 +417,7 @@
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#define MI_COM_DATA_MASK 0x0000ffff
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#define MAC_MI_STAT 0x00000450
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#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
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#define MAC_MI_STAT_10MBPS_MODE 0x00000002
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#define MAC_MI_MODE 0x00000454
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#define MAC_MI_MODE_CLK_10MHZ 0x00000001
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#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
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@ -542,6 +543,100 @@
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#define MAC_PHYCFG1_TXC_DRV 0x20000000
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#define MAC_PHYCFG2 0x000005a4
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#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
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#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
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#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
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#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
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#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
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#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
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#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
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#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
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#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
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#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
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#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
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#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
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#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
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#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
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#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
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#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
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#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
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#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
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#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
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#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
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#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
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#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
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#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
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#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
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#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
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#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
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#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
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#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
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#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
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#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
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#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
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#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
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#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
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#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
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#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
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#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
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#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
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#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
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#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
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#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
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#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
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#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
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#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
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#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
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#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
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#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
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#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
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#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
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#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
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#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
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#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
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#define MAC_PHYCFG2_50610_LED_MODES \
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(MAC_PHYCFG2_EMODE_MASK_50610 | \
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MAC_PHYCFG2_EMODE_COMP_50610 | \
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MAC_PHYCFG2_FMODE_MASK_50610 | \
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MAC_PHYCFG2_FMODE_COMP_50610 | \
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MAC_PHYCFG2_GMODE_MASK_50610 | \
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MAC_PHYCFG2_GMODE_COMP_50610 | \
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MAC_PHYCFG2_ACT_MASK_50610 | \
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MAC_PHYCFG2_ACT_COMP_50610 | \
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MAC_PHYCFG2_QUAL_MASK_50610 | \
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MAC_PHYCFG2_QUAL_COMP_50610)
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#define MAC_PHYCFG2_AC131_LED_MODES \
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(MAC_PHYCFG2_EMODE_MASK_AC131 | \
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MAC_PHYCFG2_EMODE_COMP_AC131 | \
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MAC_PHYCFG2_FMODE_MASK_AC131 | \
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MAC_PHYCFG2_FMODE_COMP_AC131 | \
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MAC_PHYCFG2_GMODE_MASK_AC131 | \
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MAC_PHYCFG2_GMODE_COMP_AC131 | \
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MAC_PHYCFG2_ACT_MASK_AC131 | \
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MAC_PHYCFG2_ACT_COMP_AC131 | \
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MAC_PHYCFG2_QUAL_MASK_AC131 | \
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MAC_PHYCFG2_QUAL_COMP_AC131)
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#define MAC_PHYCFG2_RTL8211C_LED_MODES \
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(MAC_PHYCFG2_EMODE_MASK_RT8211 | \
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MAC_PHYCFG2_EMODE_COMP_RT8211 | \
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MAC_PHYCFG2_FMODE_MASK_RT8211 | \
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MAC_PHYCFG2_FMODE_COMP_RT8211 | \
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MAC_PHYCFG2_GMODE_MASK_RT8211 | \
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MAC_PHYCFG2_GMODE_COMP_RT8211 | \
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MAC_PHYCFG2_ACT_MASK_RT8211 | \
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MAC_PHYCFG2_ACT_COMP_RT8211 | \
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MAC_PHYCFG2_QUAL_MASK_RT8211 | \
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MAC_PHYCFG2_QUAL_COMP_RT8211)
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#define MAC_PHYCFG2_RTL8201E_LED_MODES \
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(MAC_PHYCFG2_EMODE_MASK_RT8201 | \
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MAC_PHYCFG2_EMODE_COMP_RT8201 | \
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MAC_PHYCFG2_FMODE_MASK_RT8201 | \
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MAC_PHYCFG2_FMODE_COMP_RT8201 | \
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MAC_PHYCFG2_GMODE_MASK_RT8201 | \
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MAC_PHYCFG2_GMODE_COMP_RT8201 | \
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MAC_PHYCFG2_ACT_MASK_RT8201 | \
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MAC_PHYCFG2_ACT_COMP_RT8201 | \
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MAC_PHYCFG2_QUAL_MASK_RT8201 | \
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MAC_PHYCFG2_QUAL_COMP_RT8201)
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#define MAC_EXT_RGMII_MODE 0x000005a8
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#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
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#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
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@ -2595,6 +2690,8 @@ struct tg3 {
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#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
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#define TG3_PHY_ID_BCM50610 0x143bd60
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#define TG3_PHY_ID_BCMAC131 0x143bc70
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#define TG3_PHY_ID_RTL8211C 0x001cc910
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#define TG3_PHY_ID_RTL8201E 0x00008200
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#define TG3_PHY_OUI_MASK 0xfffffc00
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#define TG3_PHY_OUI_1 0x00206000
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#define TG3_PHY_OUI_2 0x0143bc00
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