Merge branch 'features/imx27-dt' of git://git.pengutronix.de/git/imx/linux-2.6 into next/dt
* 'features/imx27-dt' of git://git.pengutronix.de/git/imx/linux-2.6: devicetree-bindings: Add documentation for i.MX generic boards ARM i.MX: Add phytec phycore-i.MX27 (aka pcm038) devicetree support ARM i.MX27: Add devicetree support
This commit is contained in:
Arnd Bergmann
commit
fcd2a8e945
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|
@ -28,3 +28,25 @@ Required root node properties:
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i.MX6 Quad SABRE Lite Board
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Required root node properties:
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- compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
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Generic i.MX boards
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-------------------
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No iomux setup is done for these boards, so this must have been configured
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by the bootloader for boards to work with the generic bindings.
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i.MX27 generic board
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Required root node properties:
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- compatible = "fsl,imx27";
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i.MX51 generic board
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Required root node properties:
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- compatible = "fsl,imx51";
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i.MX53 generic board
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Required root node properties:
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- compatible = "fsl,imx53";
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i.MX6q generic board
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Required root node properties:
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- compatible = "fsl,imx6q";
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76
arch/arm/boot/dts/imx27-phytec-phycore.dts
Normal file
76
arch/arm/boot/dts/imx27-phytec-phycore.dts
Normal file
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@ -0,0 +1,76 @@
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/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
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||||
* http://www.opensource.org/licenses/gpl-license.html
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||||
* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "imx27.dtsi"
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/ {
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model = "Phytec pcm038";
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compatible = "phytec,imx27-pcm038", "fsl,imx27";
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memory {
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reg = <0x0 0x0>;
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};
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soc {
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aipi@10000000 { /* aipi */
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wdog@10002000 {
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status = "okay";
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};
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uart@1000a000 {
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fsl,uart-has-rtscts;
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status = "okay";
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};
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uart@1000b000 {
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fsl,uart-has-rtscts;
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status = "okay";
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};
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uart@1000c000 {
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fsl,uart-has-rtscts;
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status = "okay";
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};
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fec@1002b000 {
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status = "okay";
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};
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i2c@1001d000 {
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clock-frequency = <400000>;
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status = "okay";
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at24@4c {
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compatible = "at,24c32";
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pagesize = <32>;
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reg = <0x52>;
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};
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pcf8563@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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lm75@4a {
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compatible = "national,lm75";
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reg = <0x4a>;
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};
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};
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};
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};
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nor_flash@c0000000 {
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compatible = "cfi-flash";
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bank-width = <2>;
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reg = <0xc0000000 0x02000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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217
arch/arm/boot/dts/imx27.dtsi
Normal file
217
arch/arm/boot/dts/imx27.dtsi
Normal file
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@ -0,0 +1,217 @@
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/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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||||
* The code contained herein is licensed under the GNU General Public
|
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
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||||
*
|
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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};
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avic: avic-interrupt-controller@e0000000 {
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compatible = "fsl,imx27-avic", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10040000 0x1000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc26m {
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compatible = "fsl,imx-osc26m", "fixed-clock";
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clock-frequency = <26000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&avic>;
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ranges;
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aipi@10000000 { /* AIPI1 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10000000 0x10000000>;
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ranges;
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wdog@10002000 {
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compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
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reg = <0x10002000 0x4000>;
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interrupts = <27>;
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status = "disabled";
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};
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uart1: uart@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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status = "disabled";
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};
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uart2: uart@1000b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000b000 0x1000>;
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interrupts = <19>;
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status = "disabled";
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};
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uart3: uart@1000c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000c000 0x1000>;
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interrupts = <18>;
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status = "disabled";
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};
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uart4: uart@1000d000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000d000 0x1000>;
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interrupts = <17>;
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status = "disabled";
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};
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cspi1: cspi@1000e000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000e000 0x1000>;
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interrupts = <16>;
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status = "disabled";
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};
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cspi2: cspi@1000f000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000f000 0x1000>;
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interrupts = <15>;
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status = "disabled";
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};
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i2c1: i2c@10012000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
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reg = <0x10012000 0x1000>;
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interrupts = <12>;
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status = "disabled";
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};
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gpio1: gpio@10015000 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015000 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio2: gpio@10015100 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015100 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio3: gpio@10015200 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015200 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio4: gpio@10015300 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015300 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio5: gpio@10015400 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015400 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio6: gpio@10015500 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015500 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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cspi3: cspi@10017000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x10017000 0x1000>;
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interrupts = <6>;
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status = "disabled";
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};
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uart5: uart@1001b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001b000 0x1000>;
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interrupts = <49>;
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status = "disabled";
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};
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uart6: uart@1001c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001c000 0x1000>;
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interrupts = <48>;
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status = "disabled";
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};
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i2c2: i2c@1001d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
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reg = <0x1001d000 0x1000>;
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interrupts = <1>;
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status = "disabled";
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};
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fec: fec@1002b000 {
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compatible = "fsl,imx27-fec";
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reg = <0x1002b000 0x4000>;
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interrupts = <50>;
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status = "disabled";
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};
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};
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};
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};
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@ -376,6 +376,14 @@ config MACH_IMX27IPCAM
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Include support for IMX27 IPCAM platform. This includes specific
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configurations for the board and its peripherals.
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||||
config MACH_IMX27_DT
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bool "Support i.MX27 platforms from device tree"
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select SOC_IMX27
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select USE_OF
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help
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Include support for Freescale i.MX27 based platforms
|
||||
using the device tree for discovery
|
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endif
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|
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if ARCH_IMX_V6_V7
|
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|
|
|
|||
|
|
@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
|
|||
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
|
||||
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
|
||||
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
|
||||
obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
|
||||
|
||||
# i.MX31 based machines
|
||||
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
|
||||
|
|
@ -764,3 +765,20 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
int __init mx27_clocks_init_dt(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 fref = 26000000; /* default */
|
||||
|
||||
for_each_compatible_node(np, NULL, "fixed-clock") {
|
||||
if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
|
||||
continue;
|
||||
|
||||
if (!of_property_read_u32(np, "clock-frequency", &fref))
|
||||
break;
|
||||
}
|
||||
|
||||
return mx27_clocks_init(fref);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
89
arch/arm/mach-imx/imx27-dt.c
Normal file
89
arch/arm/mach-imx/imx27-dt.c
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* Copyright 2012 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/mx27.h>
|
||||
|
||||
static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int __init imx27_avic_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
irq_domain_add_simple(np, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init imx27_gpio_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
|
||||
|
||||
irq_domain_add_simple(np, gpio_irq_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx27_irq_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
|
||||
{ .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx27_dt_init(void)
|
||||
{
|
||||
of_irq_init(imx27_irq_match);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx27_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static void __init imx27_timer_init(void)
|
||||
{
|
||||
mx27_clocks_init_dt();
|
||||
}
|
||||
|
||||
static struct sys_timer imx27_timer = {
|
||||
.init = imx27_timer_init,
|
||||
};
|
||||
|
||||
static const char *imx27_dt_board_compat[] __initdata = {
|
||||
"fsl,imx27",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
|
||||
.map_io = mx27_map_io,
|
||||
.init_early = imx27_init_early,
|
||||
.init_irq = mx27_init_irq,
|
||||
.handle_irq = imx27_handle_irq,
|
||||
.timer = &imx27_timer,
|
||||
.init_machine = imx27_dt_init,
|
||||
.dt_compat = imx27_dt_board_compat,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
|
|
@ -65,6 +65,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
|
|||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
|
||||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mx27_clocks_init_dt(void);
|
||||
extern int mx51_clocks_init_dt(void);
|
||||
extern int mx53_clocks_init_dt(void);
|
||||
extern int mx6q_clocks_init(void);
|
||||
|
|
|
|||
Loading…
Reference in a new issue