[TG3]: use TG3_FLG2_5705_PLUS instead of multi-way if's
Replace a number of three-way if statements checking for 5705, 5750, and 5752 to reference the equivalent TG3_FLG2_5705_PLUS flag instead. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -85,9 +85,7 @@
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/* hardware minimum and maximum for a single frame's data payload */
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/* hardware minimum and maximum for a single frame's data payload */
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#define TG3_MIN_MTU 60
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#define TG3_MIN_MTU 60
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#define TG3_MAX_MTU(tp) \
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#define TG3_MAX_MTU(tp) \
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((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
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(!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
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/* These numbers seem to be hard coded in the NIC firmware somehow.
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/* These numbers seem to be hard coded in the NIC firmware somehow.
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* You can't change the ring sizes, but you can change where you place
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* You can't change the ring sizes, but you can change where you place
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@ -863,9 +861,7 @@ out:
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if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
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if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
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/* Cannot do read-modify-write on 5401 */
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/* Cannot do read-modify-write on 5401 */
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
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u32 phy_reg;
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u32 phy_reg;
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/* Set bit 14 with read-modify-write to preserve other bits */
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/* Set bit 14 with read-modify-write to preserve other bits */
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@ -877,9 +873,7 @@ out:
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/* Set phy register 0x10 bit 0 to high fifo elasticity to support
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/* Set phy register 0x10 bit 0 to high fifo elasticity to support
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* jumbo frames transmission.
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* jumbo frames transmission.
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*/
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
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u32 phy_reg;
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u32 phy_reg;
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if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
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if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
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@ -8483,9 +8477,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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/* DMA read watermark not used on PCIE */
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/* DMA read watermark not used on PCIE */
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tp->dma_rwctrl |= 0x00180000;
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tp->dma_rwctrl |= 0x00180000;
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} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
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} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->dma_rwctrl |= 0x003f0000;
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tp->dma_rwctrl |= 0x003f0000;
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else
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else
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tp->dma_rwctrl |= 0x003f000f;
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tp->dma_rwctrl |= 0x003f000f;
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