[TG3]: Add new one-shot MSI handler
Support one-shot MSI on 5787. This one-shot MSI idea is credited to David Miller. In this mode, MSI disables itself automatically after it is generated, saving the driver a register access to disable it for NAPI. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -546,6 +546,9 @@ static void tg3_enable_ints(struct tg3 *tp)
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(tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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(tp->last_tag << 24));
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if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
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tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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(tp->last_tag << 24));
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tg3_cond_int(tp);
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}
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@ -3365,6 +3368,23 @@ static inline void tg3_full_unlock(struct tg3 *tp)
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spin_unlock_bh(&tp->lock);
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}
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/* One-shot MSI handler - Chip automatically disables interrupt
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* after sending MSI so driver doesn't have to do it.
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*/
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static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct net_device *dev = dev_id;
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struct tg3 *tp = netdev_priv(dev);
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prefetch(tp->hw_status);
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prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
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if (likely(!tg3_irq_sync(tp)))
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netif_rx_schedule(dev); /* schedule NAPI poll */
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return IRQ_HANDLED;
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}
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/* MSI ISR - No need to check for interrupt sharing and no need to
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* flush status block and interrupt mailbox. PCI ordering rules
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* guarantee that MSI will arrive after the status block.
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@ -6511,6 +6531,26 @@ static void tg3_timer(unsigned long __opaque)
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add_timer(&tp->timer);
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}
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int tg3_request_irq(struct tg3 *tp)
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{
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irqreturn_t (*fn)(int, void *, struct pt_regs *);
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unsigned long flags;
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struct net_device *dev = tp->dev;
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
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fn = tg3_msi;
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if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
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fn = tg3_msi_1shot;
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flags = SA_SAMPLE_RANDOM;
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} else {
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fn = tg3_interrupt;
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if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
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fn = tg3_interrupt_tagged;
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flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
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}
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return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
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}
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static int tg3_test_interrupt(struct tg3 *tp)
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{
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struct net_device *dev = tp->dev;
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@ -6547,16 +6587,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
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free_irq(tp->pdev->irq, dev);
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
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err = request_irq(tp->pdev->irq, tg3_msi,
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SA_SAMPLE_RANDOM, dev->name, dev);
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else {
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irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
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if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
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fn = tg3_interrupt_tagged;
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err = request_irq(tp->pdev->irq, fn,
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SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
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}
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err = tg3_request_irq(tp);
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if (err)
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return err;
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@ -6608,14 +6639,7 @@ static int tg3_test_msi(struct tg3 *tp)
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tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
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{
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irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
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if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
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fn = tg3_interrupt_tagged;
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err = request_irq(tp->pdev->irq, fn,
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SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
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}
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err = tg3_request_irq(tp);
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if (err)
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return err;
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@ -6677,17 +6701,7 @@ static int tg3_open(struct net_device *dev)
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tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
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}
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}
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
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err = request_irq(tp->pdev->irq, tg3_msi,
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SA_SAMPLE_RANDOM, dev->name, dev);
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else {
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irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
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if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
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fn = tg3_interrupt_tagged;
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err = request_irq(tp->pdev->irq, fn,
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SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
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}
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err = tg3_request_irq(tp);
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if (err) {
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
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@ -6752,6 +6766,14 @@ static int tg3_open(struct net_device *dev)
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return err;
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}
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
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if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
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u32 val = tr32(0x7c04);
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tw32(0x7c04, val | (1 << 29));
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}
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}
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}
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tg3_full_lock(tp, 0);
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@ -9940,9 +9962,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
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else
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tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
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} else
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
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}
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@ -2209,6 +2209,7 @@ struct tg3 {
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#define TG3_FLG2_5780_CLASS 0x04000000
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#define TG3_FLG2_HW_TSO_2 0x08000000
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
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#define TG3_FLG2_1SHOT_MSI 0x10000000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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