powerpc/powernv/pci: Rework accessing the TCE invalidate register
It's architected, always in a known place, so there is no need to keep a separate pointer to it, we use the existing "regs", and we complement it with a real mode variant. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> # Conflicts: # arch/powerpc/platforms/powernv/pci-ioda.c # arch/powerpc/platforms/powernv/pci.h Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -1721,6 +1721,13 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
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}
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}
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static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
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bool real_mode)
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{
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return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
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(phb->regs + 0x210);
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}
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static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
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unsigned long index, unsigned long npages, bool rm)
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{
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@ -1729,9 +1736,7 @@ static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
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next);
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struct pnv_ioda_pe *pe = container_of(tgl->table_group,
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struct pnv_ioda_pe, table_group);
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__be64 __iomem *invalidate = rm ?
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(__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
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pe->phb->ioda.tce_inval_reg;
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__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
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unsigned long start, end, inc;
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start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
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@ -1809,39 +1814,36 @@ static struct iommu_table_ops pnv_ioda1_iommu_ops = {
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void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
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{
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__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
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const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
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mb(); /* Ensure previous TCE table stores are visible */
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if (rm)
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__raw_rm_writeq(cpu_to_be64(val),
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(__be64 __iomem *)
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phb->ioda.tce_inval_reg_phys);
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__raw_rm_writeq(cpu_to_be64(val), invalidate);
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else
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__raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
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__raw_writeq(cpu_to_be64(val), invalidate);
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}
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static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
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{
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/* 01xb - invalidate TCEs that match the specified PE# */
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__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
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unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
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struct pnv_phb *phb = pe->phb;
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if (!phb->ioda.tce_inval_reg)
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return;
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mb(); /* Ensure above stores are visible */
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__raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
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__raw_writeq(cpu_to_be64(val), invalidate);
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}
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static void pnv_pci_phb3_tce_invalidate(unsigned pe_number, bool rm,
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__be64 __iomem *invalidate, unsigned shift,
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unsigned long index, unsigned long npages)
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static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
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unsigned shift, unsigned long index,
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unsigned long npages)
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{
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__be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
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unsigned long start, end, inc;
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/* We'll invalidate DMA address in PE scope */
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start = PHB3_TCE_KILL_INVAL_ONE;
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start |= (pe_number & 0xFF);
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start |= (pe->pe_number & 0xFF);
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end = start;
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/* Figure out the start, end and step */
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@ -1867,10 +1869,6 @@ static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
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list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
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struct pnv_ioda_pe *pe = container_of(tgl->table_group,
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struct pnv_ioda_pe, table_group);
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__be64 __iomem *invalidate = rm ?
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(__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
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pe->phb->ioda.tce_inval_reg;
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if (pe->phb->type == PNV_PHB_NPU) {
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/*
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* The NVLink hardware does not support TCE kill
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@ -1880,9 +1878,8 @@ static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
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pnv_pci_phb3_tce_invalidate_entire(pe->phb, rm);
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continue;
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}
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pnv_pci_phb3_tce_invalidate(pe->pe_number, rm,
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invalidate, tbl->it_page_shift,
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index, npages);
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pnv_pci_phb3_tce_invalidate(pe, rm, tbl->it_page_shift,
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index, npages);
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}
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}
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@ -2467,19 +2464,6 @@ static void pnv_pci_ioda_setup_iommu_api(void)
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static void pnv_pci_ioda_setup_iommu_api(void) { };
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#endif
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static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
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{
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const __be64 *swinvp;
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/* OPAL variant of PHB3 invalidated TCEs */
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swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
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if (!swinvp)
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return;
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phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
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phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
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}
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static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
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unsigned levels, unsigned long limit,
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unsigned long *current_offset, unsigned long *total_allocated)
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@ -3459,6 +3443,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
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struct pnv_phb *phb;
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unsigned long size, m64map_off, m32map_off, pemap_off;
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unsigned long iomap_off = 0, dma32map_off = 0;
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struct resource r;
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const __be64 *prop64;
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const __be32 *prop32;
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int len;
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@ -3519,12 +3504,12 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
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pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
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/* Get registers */
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phb->regs = of_iomap(np, 0);
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if (phb->regs == NULL)
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pr_err(" Failed to map registers !\n");
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/* Initialize TCE kill register */
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pnv_pci_ioda_setup_opal_tce_kill(phb);
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if (!of_address_to_resource(np, 0, &r)) {
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phb->regs_phys = r.start;
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phb->regs = ioremap(r.start, resource_size(&r));
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if (phb->regs == NULL)
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pr_err(" Failed to map registers !\n");
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}
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/* Initialize more IODA stuff */
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phb->ioda.total_pe_num = 1;
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@ -86,6 +86,7 @@ struct pnv_phb {
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u64 opal_id;
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int flags;
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void __iomem *regs;
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u64 regs_phys;
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int initialized;
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spinlock_t lock;
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@ -162,12 +163,6 @@ struct pnv_phb {
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/* Reverse map of PEs, indexed by {bus, devfn} */
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unsigned int pe_rmap[0x10000];
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/* TCE cache invalidate registers (physical and
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* remapped)
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*/
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phys_addr_t tce_inval_reg_phys;
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__be64 __iomem *tce_inval_reg;
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} ioda;
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/* PHB and hub status structure */
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