s390/spinlock: remove unneeded serializations at unlock
the kernel locks have aqcuire/release semantics. No operation done after the lock can be "moved" before the lock and no operation before the unlock can be moved after the unlock. But it is perfectly fine that memory accesses which happen code wise after unlock are performed within the critical section. On s390x, reads are in-order with other reads (PoP section "Storage-Operand Fetch References") and writes are in-order with other writes (PoP section "Storage-Operand Store References"). Writes are also in-order with reads to the same memory location (PoP section "Storage-Operand Store References"). To other CPUs (and the channel subsystem), reads additionally appear to be performed prior to reads or writes that happen after them in the conceptual sequence (PoP section "Relation between Operand Accesses"). So at least as observed by other CPUs and the channel subsystem, reads inside the critical sections will not happen after unlock (and writes are in-order anyway). That's exactly what we need for "RELEASE operations" (memory-barriers.txt): "It guarantees that all memory operations before the RELEASE operation will appear to happen before the RELEASE operation with respect to the other components of the system." Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-By: Sascha Silbe <silbe@linux.vnet.ibm.com> [cross-reading and lot of improvements for the patch description] Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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@ -87,7 +87,6 @@ static inline void arch_spin_unlock(arch_spinlock_t *lp)
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{
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typecheck(unsigned int, lp->lock);
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asm volatile(
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__ASM_BARRIER
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"st %1,%0\n"
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: "+Q" (lp->lock)
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: "d" (0)
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@ -169,7 +168,6 @@ static inline int arch_write_trylock_once(arch_rwlock_t *rw)
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\
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typecheck(unsigned int *, ptr); \
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asm volatile( \
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"bcr 14,0\n" \
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op_string " %0,%2,%1\n" \
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: "=d" (old_val), "+Q" (*ptr) \
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: "d" (op_val) \
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@ -243,7 +241,6 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
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rw->owner = 0;
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asm volatile(
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__ASM_BARRIER
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"st %1,%0\n"
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: "+Q" (rw->lock)
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: "d" (0)
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