[PATCH] S2io: Performance improvements
Hi, This patch relates to mostly performance related changes. 1. Fixed incorrect computation of PANIC level in rx_buffer_level(). 2. Removed unnecessary PIOs(read/write of tx_traffic_int and rx_traffic_int) from interrupt handler and removed read of general_int_status register from xmit routine. 3. Enable two-buffer mode(for Rx path) automatically for SGI systems. This improves Rx performance dramatically on SGI systems. Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com> Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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@ -100,8 +100,7 @@ static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
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mac_control = &sp->mac_control;
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if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
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level = LOW;
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if ((mac_control->rings[ring].pkt_cnt - rxb_size) <
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MAX_RXDS_PER_BLOCK) {
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if (rxb_size <= MAX_RXDS_PER_BLOCK) {
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level = PANIC;
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}
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}
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@ -2193,7 +2192,6 @@ static void rx_intr_handler(ring_info_t *ring_data)
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{
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nic_t *nic = ring_data->nic;
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struct net_device *dev = (struct net_device *) nic->dev;
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XENA_dev_config_t __iomem *bar0 = nic->bar0;
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int get_block, get_offset, put_block, put_offset, ring_bufs;
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rx_curr_get_info_t get_info, put_info;
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RxD_t *rxdp;
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@ -2201,8 +2199,6 @@ static void rx_intr_handler(ring_info_t *ring_data)
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#ifndef CONFIG_S2IO_NAPI
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int pkt_cnt = 0;
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#endif
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register u64 val64;
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spin_lock(&nic->rx_lock);
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if (atomic_read(&nic->card_state) == CARD_DOWN) {
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DBG_PRINT(ERR_DBG, "%s: %s going down for reset\n",
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@ -2210,13 +2206,6 @@ static void rx_intr_handler(ring_info_t *ring_data)
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spin_unlock(&nic->rx_lock);
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}
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/*
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* rx_traffic_int reg is an R1 register, hence we read and write
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* back the same value in the register to clear it
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*/
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val64 = readq(&bar0->tx_traffic_int);
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writeq(val64, &bar0->tx_traffic_int);
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get_info = ring_data->rx_curr_get_info;
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get_block = get_info.block_index;
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put_info = ring_data->rx_curr_put_info;
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@ -2312,20 +2301,11 @@ static void rx_intr_handler(ring_info_t *ring_data)
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static void tx_intr_handler(fifo_info_t *fifo_data)
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{
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nic_t *nic = fifo_data->nic;
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XENA_dev_config_t __iomem *bar0 = nic->bar0;
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struct net_device *dev = (struct net_device *) nic->dev;
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tx_curr_get_info_t get_info, put_info;
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struct sk_buff *skb;
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TxD_t *txdlp;
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u16 j, frg_cnt;
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register u64 val64 = 0;
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/*
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* tx_traffic_int reg is an R1 register, hence we read and write
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* back the same value in the register to clear it
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*/
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val64 = readq(&bar0->tx_traffic_int);
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writeq(val64, &bar0->tx_traffic_int);
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get_info = fifo_data->tx_curr_get_info;
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put_info = fifo_data->tx_curr_put_info;
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@ -2818,7 +2798,6 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
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#endif
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mac_info_t *mac_control;
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struct config_param *config;
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XENA_dev_config_t __iomem *bar0 = sp->bar0;
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mac_control = &sp->mac_control;
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config = &sp->config;
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@ -2870,7 +2849,6 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
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}
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txdp->Control_2 |= config->tx_intr_type;
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txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
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TXD_GATHER_CODE_FIRST);
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txdp->Control_1 |= TXD_LIST_OWN_XENA;
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@ -2890,6 +2868,8 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
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val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
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writeq(val64, &tx_fifo->TxDL_Pointer);
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wmb();
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val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
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TX_FIFO_LAST_LIST);
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@ -2899,9 +2879,6 @@ int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
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#endif
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writeq(val64, &tx_fifo->List_Control);
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/* Perform a PCI read to flush previous writes */
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val64 = readq(&bar0->general_int_status);
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put_off++;
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put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
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mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
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@ -2940,7 +2917,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
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nic_t *sp = dev->priv;
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XENA_dev_config_t __iomem *bar0 = sp->bar0;
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int i;
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u64 reason = 0;
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u64 reason = 0, val64;
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mac_info_t *mac_control;
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struct config_param *config;
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@ -2978,6 +2955,13 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
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#else
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/* If Intr is because of Rx Traffic */
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if (reason & GEN_INTR_RXTRAFFIC) {
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/*
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* rx_traffic_int reg is an R1 register, writing all 1's
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* will ensure that the actual interrupt causing bit get's
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* cleared and hence a read can be avoided.
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*/
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val64 = 0xFFFFFFFFFFFFFFFFULL;
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writeq(val64, &bar0->rx_traffic_int);
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for (i = 0; i < config->rx_ring_num; i++) {
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rx_intr_handler(&mac_control->rings[i]);
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}
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@ -2986,6 +2970,14 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
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/* If Intr is because of Tx Traffic */
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if (reason & GEN_INTR_TXTRAFFIC) {
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/*
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* tx_traffic_int reg is an R1 register, writing all 1's
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* will ensure that the actual interrupt causing bit get's
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* cleared and hence a read can be avoided.
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*/
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val64 = 0xFFFFFFFFFFFFFFFFULL;
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writeq(val64, &bar0->tx_traffic_int);
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for (i = 0; i < config->tx_fifo_num; i++)
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tx_intr_handler(&mac_control->fifos[i]);
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}
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@ -13,6 +13,11 @@
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#ifndef _S2IO_H
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#define _S2IO_H
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/* Enable 2 buffer mode by default for SGI system */
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#ifdef CONFIG_IA64_SGI_SN2
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#define CONFIG_2BUFF_MODE
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#endif
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#define TBD 0
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#define BIT(loc) (0x8000000000000000ULL >> (loc))
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#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
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