[media] adv7842: set LLC DLL phase from platform_data
The correct LLC DLL phase depends on the board layout, so this should be part of the platform_data. Also updated the platform_data in ezkit to ensure that what was the old default value is now explicitly specified, so the behavior for that board is unchanged. Tested-by: Martin Bugge <marbugge@cisco.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Cc: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
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@ -1027,6 +1027,7 @@ static struct adv7842_platform_data adv7842_data = {
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.vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
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.vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
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.hdmi_free_run_enable = 1,
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.hdmi_free_run_enable = 1,
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.sdp_free_run_auto = 1,
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.sdp_free_run_auto = 1,
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.llc_dll_phase = 0x10,
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.i2c_sdp_io = 0x40,
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.i2c_sdp_io = 0x40,
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.i2c_sdp = 0x41,
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.i2c_sdp = 0x41,
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.i2c_cp = 0x42,
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.i2c_cp = 0x42,
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@ -1593,9 +1593,6 @@ static void select_input(struct v4l2_subdev *sd,
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afe_write(sd, 0x00, 0x00); /* power up ADC */
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afe_write(sd, 0x00, 0x00); /* power up ADC */
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afe_write(sd, 0xc8, 0x00); /* phase control */
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afe_write(sd, 0xc8, 0x00); /* phase control */
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io_write(sd, 0x19, 0x83); /* LLC DLL phase */
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io_write(sd, 0x33, 0x40); /* LLC DLL enable */
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io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
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io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
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/* script says register 0xde, which don't exist in manual */
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/* script says register 0xde, which don't exist in manual */
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@ -2609,8 +2606,7 @@ static int adv7842_core_init(struct v4l2_subdev *sd)
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io_write_and_or(sd, 0x20, 0xcf, 0x00);
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io_write_and_or(sd, 0x20, 0xcf, 0x00);
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/* LLC */
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/* LLC */
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/* Set phase to 16. TODO: get this from platform_data */
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io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
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io_write(sd, 0x19, 0x90);
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io_write(sd, 0x33, 0x40);
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io_write(sd, 0x33, 0x40);
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/* interrupts */
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/* interrupts */
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@ -192,6 +192,12 @@ struct adv7842_platform_data {
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unsigned sync:2;
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unsigned sync:2;
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} drive_strength;
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} drive_strength;
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/*
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* IO register 0x19: Adjustment to the LLC DLL phase in
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* increments of 1/32 of a clock period.
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*/
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unsigned llc_dll_phase:5;
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/* External RAM for 3-D comb or frame synchronizer */
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/* External RAM for 3-D comb or frame synchronizer */
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unsigned sd_ram_size; /* ram size in MB */
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unsigned sd_ram_size; /* ram size in MB */
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unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
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unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
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