Allwinner sunXi core additions for 3.12, take 2
These patches add machine support for the Allwinner A20 and A31 SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJSEx+TAAoJEBx+YmzsjxAgN6kP/2aiY4ZfRxXC5yw1RlT9de4I iy0uO+sSHevQWYvdL5sRr19kL2P1v4ZPqxZddJzgQVzpXTl9QOQrd0E0VqLgcNOI hn+HXK3jY8984xCLHaj7EMKwOtC+7IVx+xkCRqN88D8G9OuVCVx9FJAHFHQzJDK/ IMfJysuEtTMMxNmNTpGuU/1KE1OrIPr1/a17FZ3KAYjiwyf+7zHsAKQvLjgxRk8/ c5YZmiRO/DNsJ4qqQVgpfJe10WitXtsUiLNuYge0BrmCj26PxO+MQuzSh3zdLkpN 1m8egIZ9PVuIkXp1NcRNrYqnT1oEvSL0DOOnTo4rhINQbJXz2l18dsc+J8P3bcSK ONeW2vTOYAqb+ThzEUVKiKC2OiPY2jETVVvKaspZiohiLH1ABHchLTufm2/1yw/o VXLcI0VHoJG9Qyl6t+78Td9WTu7LxR5odpTGQpkBQEm//mV+nnK07BJbToNa6VeO G5mO3+/iRqQsZiZg08OCcKScqHFq9CVpOBx1ArYOKYJM8muzlvkNO19O962pQ1lh HymY1Nxg3+78SfiZuUDcuFSYEqWmlgPXw9VWbHAUdpETkBf938l9LqDkwApSkLFD UujBAPj5CuFy/KHRMd8Nbp11hThsKQTKe9vtoD8zVuQu6gmIy3gpJK5XXUhhLtsn bLnKRF3ZaO0mg8k/13BL =MCmi -----END PGP SIGNATURE----- Merge tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux into next/soc Allwinner sunXi core additions for 3.12, take 2 These patches add machine support for the Allwinner A20 and A31 SoCs * tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux: ARM: sunxi: Introduce Allwinner A20 support ARM: sun6i: Add restart code for the A31 ARM: sunxi: Add the Allwinner A31 compatible to the machine definition
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commit
fe870ae70b
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@ -1,8 +1,9 @@
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Allwinner sun4i Watchdog timer
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Allwinner SoCs Watchdog timer
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Required properties:
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- compatible : should be "allwinner,sun4i-wdt"
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- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
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SoC families being sun4i and sun6i
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- reg : Specifies base physical address and size of the registers.
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Example:
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@ -10,3 +10,5 @@ config ARCH_SUNXI
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select SPARSE_IRQ
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select SUN4I_TIMER
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select PINCTRL_SUNXI
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select ARM_GIC
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select HAVE_SMP
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@ -27,10 +27,19 @@
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#include <asm/system_misc.h>
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#define SUN4I_WATCHDOG_CTRL_REG 0x00
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#define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0)
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#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
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#define SUN4I_WATCHDOG_MODE_REG 0x04
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#define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0)
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#define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1)
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#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
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#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
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#define SUN6I_WATCHDOG1_IRQ_REG 0x00
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#define SUN6I_WATCHDOG1_CTRL_REG 0x10
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#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
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#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
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#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
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#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
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#define SUN6I_WATCHDOG1_MODE_REG 0x18
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#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
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static void __iomem *wdt_base;
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@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd)
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}
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}
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static void sun6i_restart(enum reboot_mode mode, const char *cmd)
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{
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if (!wdt_base)
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return;
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/* Disable interrupts */
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writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
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/* We want to disable the IRQ and just reset the whole system */
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writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
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wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
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/* Enable timer. The default and lowest interval value is 0.5s */
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writel(SUN6I_WATCHDOG1_MODE_ENABLE,
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wdt_base + SUN6I_WATCHDOG1_MODE_REG);
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/* Restart the watchdog. */
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writel(SUN6I_WATCHDOG1_CTRL_RESTART,
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wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
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while (1) {
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mdelay(5);
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writel(SUN6I_WATCHDOG1_MODE_ENABLE,
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wdt_base + SUN6I_WATCHDOG1_MODE_REG);
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}
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}
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static struct of_device_id sunxi_restart_ids[] = {
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{ .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
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{ .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
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{ /*sentinel*/ }
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};
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@ -96,6 +133,8 @@ static const char * const sunxi_board_dt_compat[] = {
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"allwinner,sun4i-a10",
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"allwinner,sun5i-a10s",
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"allwinner,sun5i-a13",
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"allwinner,sun6i-a31",
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"allwinner,sun7i-a20",
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NULL,
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};
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