Allwinner sunXi core additions for 3.12, take 2

These patches add machine support for the Allwinner A20 and A31 SoCs
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJSEx+TAAoJEBx+YmzsjxAgN6kP/2aiY4ZfRxXC5yw1RlT9de4I
 iy0uO+sSHevQWYvdL5sRr19kL2P1v4ZPqxZddJzgQVzpXTl9QOQrd0E0VqLgcNOI
 hn+HXK3jY8984xCLHaj7EMKwOtC+7IVx+xkCRqN88D8G9OuVCVx9FJAHFHQzJDK/
 IMfJysuEtTMMxNmNTpGuU/1KE1OrIPr1/a17FZ3KAYjiwyf+7zHsAKQvLjgxRk8/
 c5YZmiRO/DNsJ4qqQVgpfJe10WitXtsUiLNuYge0BrmCj26PxO+MQuzSh3zdLkpN
 1m8egIZ9PVuIkXp1NcRNrYqnT1oEvSL0DOOnTo4rhINQbJXz2l18dsc+J8P3bcSK
 ONeW2vTOYAqb+ThzEUVKiKC2OiPY2jETVVvKaspZiohiLH1ABHchLTufm2/1yw/o
 VXLcI0VHoJG9Qyl6t+78Td9WTu7LxR5odpTGQpkBQEm//mV+nnK07BJbToNa6VeO
 G5mO3+/iRqQsZiZg08OCcKScqHFq9CVpOBx1ArYOKYJM8muzlvkNO19O962pQ1lh
 HymY1Nxg3+78SfiZuUDcuFSYEqWmlgPXw9VWbHAUdpETkBf938l9LqDkwApSkLFD
 UujBAPj5CuFy/KHRMd8Nbp11hThsKQTKe9vtoD8zVuQu6gmIy3gpJK5XXUhhLtsn
 bLnKRF3ZaO0mg8k/13BL
 =MCmi
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux into next/soc

Allwinner sunXi core additions for 3.12, take 2

These patches add machine support for the Allwinner A20 and A31 SoCs

* tag 'sunxi-core-for-3.12-2' of https://github.com/mripard/linux:
  ARM: sunxi: Introduce Allwinner A20 support
  ARM: sun6i: Add restart code for the A31
  ARM: sunxi: Add the Allwinner A31 compatible to the machine definition

Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt

@@ -1,8 +1,9 @@
-Allwinner sun4i Watchdog timer
+Allwinner SoCs Watchdog timer
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-wdt"
+- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
+  SoC families being sun4i and sun6i
 - reg : Specifies base physical address and size of the registers.
 
 Example:

arch/arm/mach-sunxi/Kconfig

@@ -10,3 +10,5 @@ config ARCH_SUNXI
 	select SPARSE_IRQ
 	select SUN4I_TIMER
 	select PINCTRL_SUNXI
+	select ARM_GIC
+	select HAVE_SMP

arch/arm/mach-sunxi/sunxi.c

@@ -27,10 +27,19 @@
 #include <asm/system_misc.h>
 
 #define SUN4I_WATCHDOG_CTRL_REG		0x00
-#define SUN4I_WATCHDOG_CTRL_RESTART		(1 << 0)
+#define SUN4I_WATCHDOG_CTRL_RESTART		BIT(0)
 #define SUN4I_WATCHDOG_MODE_REG		0x04
-#define SUN4I_WATCHDOG_MODE_ENABLE		(1 << 0)
-#define SUN4I_WATCHDOG_MODE_RESET_ENABLE	(1 << 1)
+#define SUN4I_WATCHDOG_MODE_ENABLE		BIT(0)
+#define SUN4I_WATCHDOG_MODE_RESET_ENABLE	BIT(1)
+
+#define SUN6I_WATCHDOG1_IRQ_REG		0x00
+#define SUN6I_WATCHDOG1_CTRL_REG	0x10
+#define SUN6I_WATCHDOG1_CTRL_RESTART		BIT(0)
+#define SUN6I_WATCHDOG1_CONFIG_REG	0x14
+#define SUN6I_WATCHDOG1_CONFIG_RESTART		BIT(0)
+#define SUN6I_WATCHDOG1_CONFIG_IRQ		BIT(1)
+#define SUN6I_WATCHDOG1_MODE_REG	0x18
+#define SUN6I_WATCHDOG1_MODE_ENABLE		BIT(0)
 
 static void __iomem *wdt_base;
 
@@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd)
 	}
 }
 
+static void sun6i_restart(enum reboot_mode mode, const char *cmd)
+{
+	if (!wdt_base)
+		return;
+
+	/* Disable interrupts */
+	writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
+
+	/* We want to disable the IRQ and just reset the whole system */
+	writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
+		wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
+
+	/* Enable timer. The default and lowest interval value is 0.5s */
+	writel(SUN6I_WATCHDOG1_MODE_ENABLE,
+		wdt_base + SUN6I_WATCHDOG1_MODE_REG);
+
+	/* Restart the watchdog. */
+	writel(SUN6I_WATCHDOG1_CTRL_RESTART,
+		wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
+
+	while (1) {
+		mdelay(5);
+		writel(SUN6I_WATCHDOG1_MODE_ENABLE,
+			wdt_base + SUN6I_WATCHDOG1_MODE_REG);
+	}
+}
+
 static struct of_device_id sunxi_restart_ids[] = {
 	{ .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
+	{ .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
 	{ /*sentinel*/ }
 };
 
@@ -96,6 +133,8 @@ static const char * const sunxi_board_dt_compat[] = {
 	"allwinner,sun4i-a10",
 	"allwinner,sun5i-a10s",
 	"allwinner,sun5i-a13",
+	"allwinner,sun6i-a31",
+	"allwinner,sun7i-a20",
 	NULL,
 };