[ARM] OMAP: Fix sparse, checkpatch warnings in OMAP2/3 PRCM/PM code
Fix sparse & checkpatch warnings in OMAP2/3 PRCM & PM code. This mostly consists of: - converting pointer comparisons to integers in form similar to (ptr == 0) to the standard idiom (!ptr) - labeling a few non-static private functions as static - adding prototypes for *_init() functions in the appropriate header files, and getting rid of the corresponding open-coded extern prototypes in other C files - renaming the variable 'sclk' in mach-omap2/clock.c:omap2_get_apll_clkin to avoid shadowing an earlier declaration Clean up checkpatch issues. This mostly involves: - converting some asm/ includes to linux/ includes - cleaning up some whitespace - getting rid of braces for conditionals with single following statements Also take care of a few odds and ends, including: - getting rid of unlikely() and likely() - none of this code is particularly fast-path code, so the performance impact seems slim; and some of those likely() and unlikely() indicators are probably not as accurate as the ARM's branch predictor - removing some superfluous casts linux-omap source commit is 347df59f5d20fdf905afbc26b1328b0e28a8a01b. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
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16c90f0200
commit
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@ -26,7 +26,6 @@
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#include <mach/clock.h>
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#include <mach/clockdomain.h>
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#include <mach/sram.h>
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#include <mach/cpu.h>
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#include <asm/div64.h>
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@ -187,11 +186,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
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* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
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* 34xx reverses this, just to keep us on our toes
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*/
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if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
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if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
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ena = mask;
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} else if (cpu_mask & RATE_IN_343X) {
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else if (cpu_mask & RATE_IN_343X)
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ena = 0;
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}
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/* Wait for lock */
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while (((__raw_readl(reg) & mask) != ena) &&
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@ -267,7 +265,7 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk)
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{
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int ret;
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if (unlikely(clk->enable_reg == NULL)) {
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if (!clk->enable_reg) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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clk->name);
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return 0; /* REVISIT: -EINVAL */
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@ -283,7 +281,7 @@ static void omap2_dflt_clk_disable(struct clk *clk)
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{
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u32 regval32;
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if (clk->enable_reg == NULL) {
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if (!clk->enable_reg) {
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/*
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* 'Independent' here refers to a clock which is not
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* controlled by its parent.
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@ -330,7 +328,7 @@ void omap2_clk_disable(struct clk *clk)
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{
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if (clk->usecount > 0 && !(--clk->usecount)) {
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_omap2_clk_disable(clk);
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if (likely((u32)clk->parent))
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if (clk->parent)
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omap2_clk_disable(clk->parent);
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if (clk->clkdm)
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omap2_clkdm_clk_disable(clk->clkdm, clk);
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@ -343,10 +341,10 @@ int omap2_clk_enable(struct clk *clk)
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int ret = 0;
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if (clk->usecount++ == 0) {
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if (likely((u32)clk->parent))
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if (clk->parent)
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ret = omap2_clk_enable(clk->parent);
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if (unlikely(ret != 0)) {
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if (ret != 0) {
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clk->usecount--;
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return ret;
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}
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@ -356,7 +354,7 @@ int omap2_clk_enable(struct clk *clk)
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ret = _omap2_clk_enable(clk);
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if (unlikely(ret != 0)) {
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if (ret != 0) {
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if (clk->clkdm)
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omap2_clkdm_clk_disable(clk->clkdm, clk);
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@ -384,7 +382,7 @@ void omap2_clksel_recalc(struct clk *clk)
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if (div == 0)
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return;
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if (unlikely(clk->rate == clk->parent->rate / div))
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if (clk->rate == (clk->parent->rate / div))
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return;
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clk->rate = clk->parent->rate / div;
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@ -400,8 +398,8 @@ void omap2_clksel_recalc(struct clk *clk)
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* the element associated with the supplied parent clock address.
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* Returns a pointer to the struct clksel on success or NULL on error.
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*/
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const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
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struct clk *src_clk)
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static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
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struct clk *src_clk)
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{
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const struct clksel *clks;
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@ -450,7 +448,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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*new_div = 1;
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clks = omap2_get_clksel_by_parent(clk, clk->parent);
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if (clks == NULL)
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if (!clks)
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return ~0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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@ -509,7 +507,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
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/* Given a clock and a rate apply a clock specific rounding function */
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk->round_rate != NULL)
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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if (clk->flags & RATE_FIXED)
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@ -535,7 +533,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
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const struct clksel_rate *clkr;
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clks = omap2_get_clksel_by_parent(clk, clk->parent);
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if (clks == NULL)
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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@ -571,7 +569,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
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WARN_ON(div == 0);
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clks = omap2_get_clksel_by_parent(clk, clk->parent);
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if (clks == NULL)
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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@ -596,9 +594,9 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
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*
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* Returns the address of the clksel register upon success or NULL on error.
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*/
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void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
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static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
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{
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if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
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if (!clk->clksel_reg || (clk->clksel_mask == 0))
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return NULL;
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*field_mask = clk->clksel_mask;
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@ -618,7 +616,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
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void __iomem *div_addr;
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div_addr = omap2_get_clksel(clk, &field_mask);
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if (div_addr == NULL)
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if (!div_addr)
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return 0;
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field_val = __raw_readl(div_addr) & field_mask;
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@ -637,7 +635,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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return -EINVAL;
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div_addr = omap2_get_clksel(clk, &field_mask);
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if (div_addr == NULL)
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if (!div_addr)
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return -EINVAL;
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field_val = omap2_divisor_to_clksel(clk, new_div);
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@ -675,7 +673,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
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return -EINVAL;
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/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
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if (clk->set_rate != NULL)
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if (clk->set_rate)
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ret = clk->set_rate(clk, rate);
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return ret;
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@ -696,7 +694,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
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*src_addr = NULL;
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clks = omap2_get_clksel_by_parent(clk, src_clk);
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if (clks == NULL)
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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@ -726,7 +724,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
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void __iomem *src_addr;
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u32 field_val, field_mask, reg_val, parent_div;
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if (unlikely(clk->flags & CONFIG_PARTICIPANT))
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if (clk->flags & CONFIG_PARTICIPANT)
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return -EINVAL;
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if (!clk->clksel)
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@ -734,7 +732,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
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field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
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&field_mask, clk, &parent_div);
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if (src_addr == NULL)
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if (!src_addr)
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return -EINVAL;
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if (clk->usecount > 0)
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@ -794,7 +792,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
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return 0;
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}
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static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
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static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
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unsigned int m, unsigned int n)
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{
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unsigned long long num;
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@ -27,7 +27,7 @@ void omap2_clk_disable(struct clk *clk);
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
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int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
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int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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@ -339,7 +339,7 @@ static const struct clkops clkops_fixed = {
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* Uses the current prcm set to tell if a rate is valid.
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* You can go slower, but not faster within a given rate set.
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*/
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long omap2_dpllcore_round_rate(unsigned long target_rate)
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static long omap2_dpllcore_round_rate(unsigned long target_rate)
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{
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u32 high, low, core_clk_src;
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@ -550,7 +550,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
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/* Major subsystem dividers */
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tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
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cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
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cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
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CM_CLKSEL1);
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if (cpu_is_omap2430())
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cm_write_mod_reg(prcm->cm_clksel_mdm,
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OMAP2430_MDM_MOD, CM_CLKSEL);
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static u32 omap2_get_apll_clkin(void)
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{
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u32 aplls, sclk = 0;
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u32 aplls, srate = 0;
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aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
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aplls &= OMAP24XX_APLLS_CLKIN_MASK;
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aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
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if (aplls == APLLS_CLKIN_19_2MHZ)
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sclk = 19200000;
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srate = 19200000;
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else if (aplls == APLLS_CLKIN_13MHZ)
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sclk = 13000000;
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srate = 13000000;
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else if (aplls == APLLS_CLKIN_12MHZ)
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sclk = 12000000;
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srate = 12000000;
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return sclk;
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return srate;
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}
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static u32 omap2_get_sysclkdiv(void)
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@ -103,7 +103,7 @@ static struct platform_suspend_ops omap_pm_ops = {
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.valid = suspend_valid_only_mem,
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};
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int __init omap2_pm_init(void)
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static int __init omap2_pm_init(void)
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{
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return 0;
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}
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@ -113,12 +113,12 @@ struct clk_functions {
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extern unsigned int mpurate;
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extern int clk_init(struct clk_functions * custom_clocks);
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extern int clk_init(struct clk_functions *custom_clocks);
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extern int clk_register(struct clk *clk);
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extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern void recalculate_root_clocks(void);
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extern void followparent_recalc(struct clk * clk);
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extern void followparent_recalc(struct clk *clk);
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extern int clk_get_usecount(struct clk *clk);
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extern void clk_enable_init_clocks(void);
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@ -145,6 +145,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
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int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
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@ -20,10 +20,11 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
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#define __ASM_ARM_ARCH_DPM_PRCM_H
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#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
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#define __ASM_ARM_ARCH_OMAP_PRCM_H
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u32 omap_prcm_get_reset_sources(void);
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void omap_prcm_arch_reset(char mode);
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#endif
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@ -9,12 +9,12 @@
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <mach/prcm.h>
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#ifndef CONFIG_MACH_VOICEBLUE
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#define voiceblue_reset() do {} while (0)
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#endif
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extern void omap_prcm_arch_reset(char mode);
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static inline void arch_idle(void)
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{
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cpu_do_idle();
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