dma: tegra: enable/disable dma clock
Enable the DMA clock when allocating channel and disable clock when freeing channels. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
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dbde5c2934
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@ -1119,15 +1119,21 @@ struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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struct tegra_dma *tdma = tdc->tdma;
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int ret;
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dma_cookie_init(&tdc->dma_chan);
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tdc->config_init = false;
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return 0;
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ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0)
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dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
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return ret;
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}
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static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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struct tegra_dma *tdma = tdc->tdma;
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struct tegra_dma_desc *dma_desc;
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struct tegra_dma_sg_req *sg_req;
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@ -1163,6 +1169,7 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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list_del(&sg_req->node);
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kfree(sg_req);
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}
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clk_disable_unprepare(tdma->dma_clk);
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}
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/* Tegra20 specific DMA controller information */
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@ -1255,6 +1262,13 @@ static int __devinit tegra_dma_probe(struct platform_device *pdev)
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}
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}
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/* Enable clock before accessing registers */
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ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
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goto err_pm_disable;
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}
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/* Reset DMA controller */
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tegra_periph_reset_assert(tdma->dma_clk);
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udelay(2);
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@ -1265,6 +1279,8 @@ static int __devinit tegra_dma_probe(struct platform_device *pdev)
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
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clk_disable_unprepare(tdma->dma_clk);
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INIT_LIST_HEAD(&tdma->dma_dev.channels);
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for (i = 0; i < cdata->nr_channels; i++) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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