usb: phy: msm: Remove unused pclk_src_name
There are no references to 'pclk_src_name' in plaform code, so it is unused. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -464,9 +464,6 @@ static int msm_otg_suspend(struct msm_otg *motg)
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if (!IS_ERR(motg->core_clk))
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clk_disable_unprepare(motg->core_clk);
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if (!IS_ERR(motg->pclk_src))
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clk_disable_unprepare(motg->pclk_src);
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if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
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motg->pdata->otg_control == OTG_PMIC_CONTROL) {
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msm_hsusb_ldo_set_mode(motg, 0);
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@ -496,9 +493,6 @@ static int msm_otg_resume(struct msm_otg *motg)
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if (!atomic_read(&motg->in_lpm))
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return 0;
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if (!IS_ERR(motg->pclk_src))
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clk_prepare_enable(motg->pclk_src);
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clk_prepare_enable(motg->pclk);
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clk_prepare_enable(motg->clk);
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if (!IS_ERR(motg->core_clk))
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@ -1396,17 +1390,8 @@ static int msm_otg_probe(struct platform_device *pdev)
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* If USB Core is running its protocol engine based on CORE CLK,
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* CORE CLK must be running at >55Mhz for correct HSUSB
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* operation and USB core cannot tolerate frequency changes on
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* CORE CLK. For such USB cores, vote for maximum clk frequency
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* on pclk source
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* CORE CLK.
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*/
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motg->pclk_src = ERR_PTR(-ENOENT);
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if (motg->pdata->pclk_src_name) {
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motg->pclk_src = devm_clk_get(&pdev->dev,
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motg->pdata->pclk_src_name);
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if (IS_ERR(motg->pclk_src))
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return PTR_ERR(motg->pclk_src);
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}
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motg->pclk = devm_clk_get(&pdev->dev, "usb_hs_pclk");
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if (IS_ERR(motg->pclk)) {
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dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
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@ -1446,10 +1431,6 @@ static int msm_otg_probe(struct platform_device *pdev)
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motg->v1p8 = regs[2].consumer;
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clk_set_rate(motg->clk, 60000000);
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if (!IS_ERR(motg->pclk_src)) {
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clk_set_rate(motg->pclk_src, INT_MAX);
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clk_prepare_enable(motg->pclk_src);
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}
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clk_prepare_enable(motg->clk);
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clk_prepare_enable(motg->pclk);
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@ -1525,8 +1506,6 @@ disable_clks:
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clk_disable_unprepare(motg->clk);
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if (!IS_ERR(motg->core_clk))
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clk_disable_unprepare(motg->core_clk);
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if (!IS_ERR(motg->pclk_src))
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clk_disable_unprepare(motg->pclk_src);
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return ret;
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}
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@ -1571,9 +1550,6 @@ static int msm_otg_remove(struct platform_device *pdev)
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clk_disable_unprepare(motg->clk);
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if (!IS_ERR(motg->core_clk))
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clk_disable_unprepare(motg->core_clk);
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if (!IS_ERR(motg->pclk_src))
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clk_disable_unprepare(motg->pclk_src);
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msm_hsusb_ldo_init(motg, 0);
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pm_runtime_set_suspended(&pdev->dev);
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@ -106,8 +106,6 @@ enum usb_chg_type {
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* @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
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* @mode: Supported mode (OTG/peripheral/host).
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* @otg_control: OTG switch controlled by user/Id pin
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* @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
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* dfab_usb_hs_clk in case of 8660 and 8960.
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*/
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struct msm_otg_platform_data {
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int *phy_init_seq;
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@ -117,7 +115,6 @@ struct msm_otg_platform_data {
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enum otg_control_type otg_control;
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enum msm_usb_phy_type phy_type;
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void (*setup_gpio)(enum usb_otg_state state);
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char *pclk_src_name;
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int (*link_clk_reset)(struct clk *link_clk, bool assert);
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int (*phy_clk_reset)(struct clk *phy_clk);
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};
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@ -129,7 +126,6 @@ struct msm_otg_platform_data {
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* @irq: IRQ number assigned for HSUSB controller.
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* @clk: clock struct of usb_hs_clk.
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* @pclk: clock struct of usb_hs_pclk.
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* @pclk_src: pclk source for voting.
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* @phy_reset_clk: clock struct of usb_phy_clk.
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* @core_clk: clock struct of usb_hs_core_clk.
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* @regs: ioremapped register base address.
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@ -150,7 +146,6 @@ struct msm_otg {
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int irq;
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struct clk *clk;
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struct clk *pclk;
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struct clk *pclk_src;
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struct clk *phy_reset_clk;
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struct clk *core_clk;
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void __iomem *regs;
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