ncr5380: Implement NCR5380_dma_xfer_len and remove LIMIT_TRANSFERSIZE macro
Follow the example of the atari_NCR5380.c core driver and adopt the NCR5380_dma_xfer_len() hook. Implement NCR5380_dma_xfer_len() for dtc.c and g_NCR5380.c to take care of the limitations of these cards. Keep the default for drivers using PSEUDO_DMA. Eliminate the unused macro LIMIT_TRANSFERSIZE. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.com> Tested-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -201,11 +201,6 @@
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* DONT_USE_INTR - if defined, never use interrupts, even if we probe or
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* DONT_USE_INTR - if defined, never use interrupts, even if we probe or
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* override-configure an IRQ.
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* override-configure an IRQ.
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*
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*
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* LIMIT_TRANSFERSIZE - if defined, limit the pseudo-dma transfers to 512
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* bytes at a time. Since interrupts are disabled by default during
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* these transfers, we might need this to give reasonable interrupt
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* service time if the transfer size gets too large.
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*
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* LINKED - if defined, linked commands are supported.
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* LINKED - if defined, linked commands are supported.
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*
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*
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* PSEUDO_DMA - if defined, PSEUDO DMA is used during the data transfer phases.
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* PSEUDO_DMA - if defined, PSEUDO DMA is used during the data transfer phases.
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@ -2000,29 +1995,12 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance) {
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*/
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*/
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#if defined(PSEUDO_DMA) || defined(REAL_DMA_POLL)
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#if defined(PSEUDO_DMA) || defined(REAL_DMA_POLL)
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/* KLL
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transfersize = 0;
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* PSEUDO_DMA is defined here. If this is the g_NCR5380
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if (!cmd->device->borken &&
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* driver then it will always be defined, so the
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!(hostdata->flags & FLAG_NO_PSEUDO_DMA))
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* FLAG_NO_PSEUDO_DMA is used to inhibit PDMA in the base
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transfersize = NCR5380_dma_xfer_len(instance, cmd, phase);
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* NCR5380 case. I think this is a fairly clean solution.
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* We supplement these 2 if's with the flag.
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*/
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#ifdef NCR5380_dma_xfer_len
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if (!cmd->device->borken && !(hostdata->flags & FLAG_NO_PSEUDO_DMA) && (transfersize = NCR5380_dma_xfer_len(instance, cmd)) != 0) {
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#else
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transfersize = cmd->transfersize;
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#ifdef LIMIT_TRANSFERSIZE /* If we have problems with interrupt service */
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if (transfersize) {
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if (transfersize > 512)
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transfersize = 512;
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#endif /* LIMIT_TRANSFERSIZE */
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if (!cmd->device->borken && transfersize && !(hostdata->flags & FLAG_NO_PSEUDO_DMA) && cmd->SCp.this_residual && !(cmd->SCp.this_residual % transfersize)) {
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/* Limit transfers to 32K, for xx400 & xx406
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* pseudoDMA that transfers in 128 bytes blocks. */
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if (transfersize > 32 * 1024)
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transfersize = 32 * 1024;
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#endif
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len = transfersize;
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len = transfersize;
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if (NCR5380_transfer_dma(instance, &phase, &len, (unsigned char **) &cmd->SCp.ptr)) {
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if (NCR5380_transfer_dma(instance, &phase, &len, (unsigned char **) &cmd->SCp.ptr)) {
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/*
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/*
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@ -22,6 +22,9 @@
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#define priv(host) ((struct NCR5380_hostdata *)(host)->hostdata)
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#define priv(host) ((struct NCR5380_hostdata *)(host)->hostdata)
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#define NCR5380_read(reg) cumanascsi_read(instance, reg)
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#define NCR5380_read(reg) cumanascsi_read(instance, reg)
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#define NCR5380_write(reg, value) cumanascsi_write(instance, reg, value)
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#define NCR5380_write(reg, value) cumanascsi_write(instance, reg, value)
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_intr cumanascsi_intr
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#define NCR5380_intr cumanascsi_intr
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#define NCR5380_queue_command cumanascsi_queue_command
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#define NCR5380_queue_command cumanascsi_queue_command
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#define NCR5380_info cumanascsi_info
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#define NCR5380_info cumanascsi_info
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@ -26,6 +26,8 @@
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#define NCR5380_write(reg, value) \
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#define NCR5380_write(reg, value) \
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writeb(value, priv(instance)->base + ((reg) << 2))
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writeb(value, priv(instance)->base + ((reg) << 2))
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_queue_command oakscsi_queue_command
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#define NCR5380_queue_command oakscsi_queue_command
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#define NCR5380_info oakscsi_info
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#define NCR5380_info oakscsi_info
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#define NCR5380_show_info oakscsi_show_info
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#define NCR5380_show_info oakscsi_show_info
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@ -2170,11 +2170,13 @@ static void NCR5380_information_transfer(struct Scsi_Host *instance)
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*/
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*/
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#if defined(REAL_DMA)
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#if defined(REAL_DMA)
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if (
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#if !defined(CONFIG_SUN3)
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#if !defined(CONFIG_SUN3)
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!cmd->device->borken &&
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transfersize = 0;
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if (!cmd->device->borken)
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#endif
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#endif
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(transfersize = NCR5380_dma_xfer_len(instance, cmd, phase)) >= DMA_MIN_SIZE) {
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transfersize = NCR5380_dma_xfer_len(instance, cmd, phase);
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if (transfersize >= DMA_MIN_SIZE) {
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len = transfersize;
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len = transfersize;
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cmd->SCp.phase = phase;
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cmd->SCp.phase = phase;
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if (NCR5380_transfer_dma(instance, &phase,
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if (NCR5380_transfer_dma(instance, &phase,
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@ -419,6 +419,20 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
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return (0);
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return (0);
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}
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}
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static int dtc_dma_xfer_len(struct scsi_cmnd *cmd)
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{
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int transfersize = cmd->transfersize;
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/* Limit transfers to 32K, for xx400 & xx406
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* pseudoDMA that transfers in 128 bytes blocks.
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*/
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if (transfersize > 32 * 1024 && cmd->SCp.this_residual &&
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!(cmd->SCp.this_residual % transfersize))
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transfersize = 32 * 1024;
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return transfersize;
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}
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MODULE_LICENSE("GPL");
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MODULE_LICENSE("GPL");
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#include "NCR5380.c"
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#include "NCR5380.c"
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@ -27,6 +27,9 @@
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#define NCR5380_read(reg) (readb(DTC_address(reg)))
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#define NCR5380_read(reg) (readb(DTC_address(reg)))
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#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
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#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
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#define NCR5380_dma_xfer_len(instance, cmd, phase) \
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dtc_dma_xfer_len(cmd)
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#define NCR5380_intr dtc_intr
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#define NCR5380_intr dtc_intr
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#define NCR5380_queue_command dtc_queue_command
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#define NCR5380_queue_command dtc_queue_command
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#define NCR5380_abort dtc_abort
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#define NCR5380_abort dtc_abort
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@ -699,6 +699,21 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
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; // TIMEOUT
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; // TIMEOUT
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return 0;
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return 0;
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}
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}
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static int generic_NCR5380_dma_xfer_len(struct scsi_cmnd *cmd)
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{
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int transfersize = cmd->transfersize;
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/* Limit transfers to 32K, for xx400 & xx406
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* pseudoDMA that transfers in 128 bytes blocks.
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*/
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if (transfersize > 32 * 1024 && cmd->SCp.this_residual &&
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!(cmd->SCp.this_residual % transfersize))
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transfersize = 32 * 1024;
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return transfersize;
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}
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#endif /* PSEUDO_DMA */
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#endif /* PSEUDO_DMA */
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/*
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/*
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@ -73,6 +73,9 @@
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#endif
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#endif
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#define NCR5380_dma_xfer_len(instance, cmd, phase) \
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generic_NCR5380_dma_xfer_len(cmd)
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#define NCR5380_intr generic_NCR5380_intr
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#define NCR5380_intr generic_NCR5380_intr
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#define NCR5380_queue_command generic_NCR5380_queue_command
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#define NCR5380_queue_command generic_NCR5380_queue_command
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#define NCR5380_abort generic_NCR5380_abort
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#define NCR5380_abort generic_NCR5380_abort
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@ -38,6 +38,7 @@
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#define NCR5380_pread macscsi_pread
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#define NCR5380_pread macscsi_pread
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#define NCR5380_pwrite macscsi_pwrite
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#define NCR5380_pwrite macscsi_pwrite
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_intr macscsi_intr
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#define NCR5380_intr macscsi_intr
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#define NCR5380_queue_command macscsi_queue_command
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#define NCR5380_queue_command macscsi_queue_command
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@ -110,6 +110,8 @@
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#define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
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#define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
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#define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
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#define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_intr pas16_intr
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#define NCR5380_intr pas16_intr
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#define NCR5380_queue_command pas16_queue_command
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#define NCR5380_queue_command pas16_queue_command
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#define NCR5380_abort pas16_abort
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#define NCR5380_abort pas16_abort
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@ -84,6 +84,8 @@
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#define NCR5380_read(reg) readb(T128_address(reg))
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#define NCR5380_read(reg) readb(T128_address(reg))
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#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
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#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
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#define NCR5380_dma_xfer_len(instance, cmd, phase) (cmd->transfersize)
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#define NCR5380_intr t128_intr
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#define NCR5380_intr t128_intr
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#define NCR5380_queue_command t128_queue_command
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#define NCR5380_queue_command t128_queue_command
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#define NCR5380_abort t128_abort
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#define NCR5380_abort t128_abort
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