i.MX8MM shares same cpu-freq driver with i.MX8MQ, but
its EVK board has a PMIC which can scale VDD_ARM voltage
according to voltage defined in dtb, add support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
On i.MX8MQ, since the OPP table is initialized in cpu-freq platform
device register according to chip type, so no need to redo the OPP
table initialization in cpu-freq driver, this patch adds check for
OPP table initialization to avoid below warning during boot up:
[ 1.468378] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 1501
[ 1.468388] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 1301
[ 1.468417] cpu cpu0: _of_add_opp_table_v1: Failed to add OPP 1300000000
[ 1.468425] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 1001
[ 1.468434] cpu cpu0: _opp_add: duplicate OPPs detected. Existing: freq: 8001
[ 1.468443] cpu cpu0: _of_add_opp_table_v1: Failed to add OPP 800000000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
For i.MX8MQ, suspend freq can use policy->max after cpu freq
table is validated, so no need to get OPP number and MAX
frequency for suspend freq now, also add necessary resource free
when probe failed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
i.MX8MQ can run at over-drive mode which needs
increasing VDD_ARM voltage, add gpio regulator support
for over-drive mode.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MQ cooling device support, when temperature
exceeds passive threshold, cpu-freq will drop to lowest
set-point, and once temperature drops below passive
threshold, cpu-freq will restore.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MQ cpufreq support, current version of
EVK board does NOT support voltage scale, but next
version will add this support, so this driver only
supports cpu frequency scale, voltage scale will
be added later once new board available.
A53 CPU clock normally is from ARM_PLL, but during
ARM_PLL relock window, it will be switched to
SYS1_PLL_800M to avoid clock missing, and after
arm pll relock done, it will be switched back.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Bai Ping