There is one potential race condition in virt-dma framework as below:
terminate dma channel after the last dma done interrupt, but before
vchan_complete tasklet scheduled, thus the free-ed 'vd' (free in
fsl_edma3_terminate_all) maybe still be touched in vchan_complete()
which cause NULL pointer crash.
Kernel community noticed this issue and fix it at virt-dma level:
https://patchwork.kernel.org/patch/10057791/. To avoid backport too
much patches, set 'vc->cyclic = NULL' in terminate dma channel
interfaces to fix such issue easily.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
The swap is swapped between the i.MX8QM RevA and RevB
this patch handle this difference to set swap correctly
otherwise, the eDMA will not work on the i.MX8QM RevB
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 5f4d3549e5f61cb8e3c14dbeb406acfcccf32886)
Add device_synchronize for edma driver, since some driver such as
Audio need it to make sure dma done callback never come out after
resource related with dma channel free-ed by Audio driver. Android
team report such issue on MA-12087.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 483519c063b08fc1ce0dd297b6c186799cf639d6)
Avoid touch unused edma channel register in susped/resume, otherwise,
kernel crash if XRDC enabled in scfw.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Fix below issue reported by Coverity, actually, don't need this
condition check here, remove it.
CID undefined (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)operator_confusion:
(16UL /* 1UL << 4 */) | (__u16)(__le16)tcd->csr is always 1/true regardless of the values of its operand.
This occurs as the logical first operand of "&&".
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add suspend to save channel registers and resume to restore them back since
edmav3 may powered off in suspend.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Since there are multi edmav3 instances on i.mx8, every edma channel name
is better unique.But so far, all edma channel name is 'edma-channel(id)-
tx',thus some edma channels which share the same channel id but different
edma instance will show the same channel name in kernel and this is not
friendly to debug in kernel.
Now the edma channel name(interrupt-names property) is define in dts
as below:
"edmaX-chanX-Xx"
| | |---> receive/transmit, r or t
| |---> channel id, the max number is 32
|---> edma controller instance, 0, 1, 2,..etc
and get below correct name with 'cat /proc/interrupts':
43: 0 0 0 0 GICv3 466 Level edma0-chan8-rx
44: 0 0 0 0 GICv3 467 Level edma0-chan9-tx
45: 79 0 0 0 GICv3 468 Level edma0-chan10-rx
46: 311 0 0 0 GICv3 469 Level edma0-chan11-tx
47: 0 0 0 0 GICv3 470 Level edma0-chan12-rx
48: 0 0 0 0 GICv3 471 Level edma0-chan13-tx
49: 0 0 0 0 GICv3 472 Level edma0-chan14-rx
50: 0 0 0 0 GICv3 473 Level edma0-chan15-tx
51: 0 0 0 0 GICv3 406 Level edma2-chan0-tx
52: 0 0 0 0 GICv3 407 Level edma2-chan1-tx
53: 0 0 0 0 GICv3 408 Level edma2-chan2-tx
54: 0 0 0 0 GICv3 409 Level edma2-chan3-tx
55: 0 0 0 0 GICv3 410 Level edma2-chan4-tx
56: 0 0 0 0 GICv3 411 Level edma2-chan5-tx
57: 0 0 0 0 GICv3 442 Level edma2-chan6-rx, edma2-chan7-tx
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
There is Audio dual fifo cause that fill fifo one by one and
loop back after every minor loop:
-- fill the first 32bit width fifo
-- fill the next 32bit width fifo
-- +MLOFF signed offset after the above two FIFOs filled
-- loop back to the first step to handle the next minor loop.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
for user and it's possible other cells maybe added to other use cases,
so combine two cells into one now, and for some special use cases such as
dual fifo property can directly be passed by one bit of cell3 rather than
another cell.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Below described in RM, otherwise, channel error status(CHa_ES)
may be triggered:
The user must clear the CHa_CSR[DONE] bit before writing the
TCDa_CSR[MAJORELINK] or TCDa_CSR[ESG] bits.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
The parameter is "is_remote", which is to use remote access for
edma, the default access is local access.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Robin Gong