epdc: Turn on regulators unconditionally
Add hack to EPDC driver to unconditionally turn on the regulators
during initialization for Kaifa testing
epdc: Set pir display configuration
First attempt at setting our display configuration, based on info sheet from E-Ink
epdc: Add waveform for our display
epdc: Move waveform to correct folder
epdc: Update EPDC driver to use correct pixels per SDCLK and data bus width
epdc: Update panel timing information based on NXP EPD calculator values
epdc: Update waveform after attempting to fix NXP's waveform converter
epdc: Bring up our panel by default
epdc: Update panel timing values based on independent calculations
epdc: Add 4bit waveform for ES103CS1
epdc: Add support for ES103CS1 display with 4bit waveforms
epdc: Add patch from NXP to use the correct mutex when panning display
epdc: Remove all traces of the 5bit waveforms
epdc: Remove EPDC powerup hack
epdc: update parameters for 85hz
epdc: undo some custom unnecessary changes
epdc: don't do a normal grayscale update just for init
epdc: fix some printing of errors
epdc: use synchronous firmware loading so users know that the EPDC is inited and can do stuff
mxc_epdc_fb: restore powerdown delay after suspend
mxc_epdc_fb: fix inverted conditional leading to endless collisions
mxc_epdc_fb: epdc driver wants pixclock in hz, not ps
mxc_epdc_fb: add support for automatically getting updated temperature from pmic
Some RGB formats fourcc definition are not precise
according to its original meaning. So make some
changes for them.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit b0b4ad680e267bdf542d2c9a3202c0192bde9cb0)
The multiple overlay layers are not used on pxp v2 and
v3 module, so remove this.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit c4fd8b36dbf9b53079d88d55ccfedde3a444ec29)
l2c210_flush_all, the underlying implementation of outer_flush_all() has the
constraint on 4.1 kernel that, it can not be called under interrupt context.
However the EPDC driver can not guarantee this condition at calling point, thus
it could cause kernel dump. This has been observed on i.MX6SL, and theorically
on other platforms like i.MX6DL (using PL310 L2 cache). So use outer_flush_range
to fix it.
Although we don't have such issue on i.MX7D (not PL310 L2), we still prefer to
use outer_flush_range() for legacy software dithering support and for easy
maintenance. Then we do the change in both EPDC driver.
------------[ cut here ]------------
Kernel BUG at 800204d8 [verbose debug info unavailable]
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
Modules linked in: galcore(O) evbug
CPU: 0 PID: 842 Comm: kworker/u3:1 Tainted: G O 4.1.8-1.0.0+ge352a0b #1
Hardware name: Freescale i.MX6 SoloLite (Device Tree)
Workqueue: EPDC Submit epdc_submit_work_func
task: a8a8f900 ti: a92a4000 task.ti: a92a4000
PC is at l2c210_flush_all+0x5c/0x60
LR is at epdc_submit_work_func+0x684/0xbf8
pc : [<800204d8>] lr : [<8030702c>] psr: 600b0013
sp : a92a5e90 ip : a9150c8c fp : a8480518
r10: a84a28c0 r9 : 00000008 r8 : a9150644
r7 : a91512e0 r6 : 0000012c r5 : a91512e0 r4 : a91512dc
r3 : a00b0013 r2 : 80b184a0 r1 : 701fe019 r0 : f4a02000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: a943404a DAC: 00000015
Process kworker/u3:1 (pid: 842, stack limit = 0xa92a4210)
Stack: (0xa92a5e90 to 0xa92a6000)
5e80: a92a5ed0 8005d058 0000bbc2 a851d4c0
5ea0: 00000000 a9150000 a8480000 a8480440 00000190 00000193 55555556 a84a28c0
5ec0: a8480518 a8500000 80b18088 a94f3900 00000000 00000000 00000190 0000012c
5ee0: a94f3900 a8480518 a87e8d80 a8479000 a845a200 00000020 00000000 a8479000
5f00: a8479000 80046458 a92a4000 a8479000 a8479014 a8479000 a87e8d98 a8479014
...
Signed-off-by: Robby Cai <robby.cai@nxp.com>
The 'CONFIG_PM_RUNTIME' has been eliminated and all the users
should use 'CONFIG_PM' directly. So do this change for epdc and
epdc-v2.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
Lars Ivar Miljeteig