60 lines
1.9 KiB
Plaintext
60 lines
1.9 KiB
Plaintext
* Clock bindings for Freescale i.MX7ULP
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i.MX7ULP Clock functions are under joint control of the System
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Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
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modules, and Core Mode Controller (CMC)1 blocks
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The clocking scheme provides clear separation between M4 domain
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and A7 domain. Except for a few clock sources shared between two
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domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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and and the Fast IRC clock (FIRCLK), clock sources and clock
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management are separated and contained within each domain.
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M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
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A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
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Note: this binding doc is only for A7 clock domain.
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Required properties:
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- compatible: Should be "fsl,imx7ulp-scg0" or "fsl,imx7ulp-scg1".
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- reg : Should contain registers location and length.
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- #clock-cells: Should be <1>.
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- clocks: Should contain the fixed input clocks.
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- clock-name: Should contain the following clock names:"cm4_rosc",
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"cm4_sosc", "cm4_sirc", "cm4_firc" for scg0.
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Or
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Should contain the following clock names:"rsoc", "sosc",
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"sirc", "firc", "upll", "mpll" for scg1.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/imx7ulp-clock.h
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for the full list of i.MX7ULP clock IDs.
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Examples:
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#include <dt-bindings/clock/imx7ulp-clock.h>
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clks: scg1@403e0000 {
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compatible = "fsl,imx7ulp-clock";
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reg = <0x403e0000 0x10000>;
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clocks = <&rsoc>, <&sosc>, <&sirc>,
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<&firc>, <&upll>, <&mpll>;
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clock-names = "rsoc", "sosc", "sirc",
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"firc", "upll", "mpll";
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#clock-cells = <1>;
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};
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usdhc1: usdhc@40380000 {
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compatible = "fsl,imx7ulp-usdhc";
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reg = <0x40380000 0x10000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&clks IMX7ULP_CLK_NIC1_DIV>,
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<&clks IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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