446 lines
9.9 KiB
C
446 lines
9.9 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <soc/imx8/sc/sci.h>
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#include "clk-imx8.h"
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/*
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* DOC: basic adjustable multiplexer clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is only affected by parent switching. No clk_set_rate support
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* parent - parent is adjustable through clk_set_parent
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*/
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struct clk_mux_scu {
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struct clk_hw hw;
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void __iomem *reg;
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u32 *table;
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u32 mask;
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u8 shift;
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u8 flags;
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u32 val;
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bool update;
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spinlock_t *lock;
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char *pd_name;
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struct generic_pm_domain *pd;
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};
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struct clk_mux_gpr_scu {
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struct clk_hw hw;
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sc_rsrc_t rsrc_id;
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sc_ctrl_t gpr_id;
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};
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struct clk_mux2_scu {
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struct clk_hw hw;
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sc_rsrc_t rsrc_id;
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sc_pm_clk_t clk_type;
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};
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#define to_clk_mux_scu(_hw) container_of(_hw, struct clk_mux_scu, hw)
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#define to_clk_mux_gpr_scu(_hw) container_of(_hw, struct clk_mux_gpr_scu, hw)
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#define to_clk_mux2_scu(_hw) container_of(_hw, struct clk_mux2_scu, hw)
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/* Get the power domain associated with the clock from the device tree. */
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static void populate_mux_pd(struct clk_mux_scu *clk)
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{
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struct device_node *np;
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struct of_phandle_args pd_args;
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np = of_find_node_by_name(NULL, clk->pd_name);
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if (np) {
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pd_args.np = np;
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pd_args.args_count = 0;
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clk->pd = genpd_get_from_provider(&pd_args);
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if (IS_ERR(clk->pd))
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pr_warn("%s: failed to get pd\n", __func__);
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}
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}
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static int check_mux_pd(struct clk_mux_scu *mux)
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{
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if (!ccm_ipc_handle)
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return -1;
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if (mux->pd == NULL && mux->pd_name)
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populate_mux_pd(mux);
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if (IS_ERR_OR_NULL(mux->pd))
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return -1;
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if (mux->pd->status != GPD_STATE_ACTIVE)
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return -1;
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return 0;
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}
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static u8 clk_mux_get_parent_scu(struct clk_hw *hw)
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{
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struct clk_mux_scu *mux = to_clk_mux_scu(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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u32 val;
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/*
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* FIXME need a mux-specific flag to determine if val is bitwise or numeric
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* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
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* to 0x7 (index starts at one)
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* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
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* val = 0x4 really means "bit 2, index starts at bit 0"
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*/
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val = mux->val >> mux->shift;
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val &= mux->mask;
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if (mux->table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (mux->table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (mux->flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (mux->flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int clk_mux_prepare_scu(struct clk_hw *hw)
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{
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struct clk_mux_scu *mux = to_clk_mux_scu(hw);
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unsigned long flags = 0;
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int ret;
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ret = check_mux_pd(mux);
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if (ret)
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return ret;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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if (mux->update) {
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clk_writel(mux->val, mux->reg);
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mux->update = 0;
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}
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return 0;
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}
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static int clk_mux_set_parent_scu(struct clk_hw *hw, u8 index)
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{
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struct clk_mux_scu *mux = to_clk_mux_scu(hw);
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unsigned long flags = 0;
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int ret;
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ret = check_mux_pd(mux);
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if (mux->table) {
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index = mux->table[index];
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} else {
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if (mux->flags & CLK_MUX_INDEX_BIT)
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index = 1 << index;
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if (mux->flags & CLK_MUX_INDEX_ONE)
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index++;
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}
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
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mux->val = mux->mask << (mux->shift + 16);
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} else {
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mux->val &= ~(mux->mask << mux->shift);
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}
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mux->val |= index << mux->shift;
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mux->update = (ret != 0);
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if (ret == 0)
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clk_writel(mux->val, mux->reg);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return 0;
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}
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const struct clk_ops clk_mux_scu_ops = {
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.prepare = clk_mux_prepare_scu,
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.get_parent = clk_mux_get_parent_scu,
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.set_parent = clk_mux_set_parent_scu,
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.determine_rate = __clk_mux_determine_rate,
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};
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const struct clk_ops clk_mux_ro_scu_ops = {
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.get_parent = clk_mux_get_parent_scu,
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};
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struct clk *clk_register_mux_table_scu(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock,
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const char *pd_name)
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{
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struct clk_mux_scu *mux;
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struct clk *clk;
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struct clk_init_data init;
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u8 width = 0;
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if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
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width = fls(mask) - ffs(mask) + 1;
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if (width + shift > 16) {
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pr_err("mux value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the mux */
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mux = kzalloc(sizeof(struct clk_mux_scu), GFP_KERNEL);
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if (!mux) {
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pr_err("%s: could not allocate mux clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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if (clk_mux_flags & CLK_MUX_READ_ONLY)
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init.ops = &clk_mux_ro_scu_ops;
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else
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init.ops = &clk_mux_scu_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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/* struct clk_mux_scu assignments */
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mux->reg = reg;
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->lock = lock;
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mux->table = table;
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mux->hw.init = &init;
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mux->pd_name = NULL;
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if (pd_name) {
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mux->pd_name = kzalloc(strlen(pd_name) + 1, GFP_KERNEL);
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strcpy(mux->pd_name, pd_name);
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}
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clk = clk_register(dev, &mux->hw);
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if (IS_ERR(clk)) {
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kfree(mux->pd_name);
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kfree(mux);
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}
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return clk;
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}
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struct clk *clk_register_mux_scu(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock,
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const char *pd_name)
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{
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u32 mask = BIT(width) - 1;
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return clk_register_mux_table_scu(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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NULL, lock, pd_name);
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}
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void clk_unregister_mux_scu(struct clk *clk)
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{
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struct clk_mux_scu *mux;
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struct clk_hw *hw;
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hw = __clk_get_hw(clk);
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if (!hw)
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return;
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mux = to_clk_mux_scu(hw);
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clk_unregister(clk);
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kfree(mux);
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}
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static u8 clk_mux_gpr_scu_get_parent(struct clk_hw *hw)
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{
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struct clk_mux_gpr_scu *gpr_mux = to_clk_mux_gpr_scu(hw);
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u32 val = 0;
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if (!ccm_ipc_handle)
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return 0;
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sc_misc_get_control(ccm_ipc_handle,
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gpr_mux->rsrc_id, gpr_mux->gpr_id, &val);
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return (u8)val;
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}
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static int clk_mux_gpr_scu_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux_gpr_scu *gpr_mux = to_clk_mux_gpr_scu(hw);
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if (!ccm_ipc_handle)
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return -1;
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sc_misc_set_control(ccm_ipc_handle,
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gpr_mux->rsrc_id, gpr_mux->gpr_id, index);
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return 0;
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}
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static const struct clk_ops clk_mux_gpr_scu_ops = {
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.get_parent = clk_mux_gpr_scu_get_parent,
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.set_parent = clk_mux_gpr_scu_set_parent,
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};
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struct clk *clk_register_mux_gpr_scu(struct device *dev, const char *name,
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const char **parents, int num_parents, spinlock_t *lock,
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sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id)
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{
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struct clk_mux_gpr_scu *gpr_scu_mux;
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struct clk *clk;
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struct clk_init_data init;
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if (!imx8_clk_is_resource_owned(rsrc_id)) {
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pr_debug("skip clk %s rsrc %d not owned\n", name, rsrc_id);
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return ERR_PTR(-ENODEV);
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}
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if (rsrc_id >= SC_R_LAST)
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return NULL;
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if (gpr_id >= SC_C_LAST)
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return NULL;
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gpr_scu_mux = kzalloc(sizeof(struct clk_mux_gpr_scu), GFP_KERNEL);
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if (!gpr_scu_mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_mux_gpr_scu_ops;
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init.parent_names = parents;
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init.num_parents = num_parents;
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init.flags |= CLK_SET_PARENT_NOCACHE;
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gpr_scu_mux->hw.init = &init;
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gpr_scu_mux->rsrc_id = rsrc_id;
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gpr_scu_mux->gpr_id = gpr_id;
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clk = clk_register(NULL, &gpr_scu_mux->hw);
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if (IS_ERR(clk))
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kfree(gpr_scu_mux);
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return clk;
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}
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static u8 clk_mux2_scu_get_parent(struct clk_hw *hw)
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{
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struct clk_mux2_scu *mux = to_clk_mux2_scu(hw);
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sc_pm_clk_parent_t parent;
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sc_err_t ret;
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if (!ccm_ipc_handle)
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return -EBUSY;
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ret = sc_pm_get_clock_parent(ccm_ipc_handle, mux->rsrc_id,
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mux->clk_type, &parent);
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if (ret != SC_ERR_NONE)
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return -EINVAL;
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return (u8)parent;
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}
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static int clk_mux2_scu_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux2_scu *mux = to_clk_mux2_scu(hw);
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sc_err_t ret;
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if (!ccm_ipc_handle)
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return -EBUSY;
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ret = sc_pm_set_clock_parent(ccm_ipc_handle, mux->rsrc_id,
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mux->clk_type, index);
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if (ret != SC_ERR_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct clk_ops clk_mux2_scu_ops = {
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.get_parent = clk_mux2_scu_get_parent,
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.set_parent = clk_mux2_scu_set_parent,
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};
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struct clk *clk_register_mux2_scu(struct device *dev, const char *name,
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const char **parents, int num_parents,
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unsigned long flags, sc_rsrc_t rsrc_id,
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sc_pm_clk_t clk_type)
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{
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struct clk_mux2_scu *mux;
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struct clk *clk;
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struct clk_init_data init;
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if (!imx8_clk_is_resource_owned(rsrc_id)) {
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pr_debug("skip clk %s rsrc %d not owned\n", name, rsrc_id);
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return ERR_PTR(-ENODEV);
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}
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if (rsrc_id >= SC_R_LAST)
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return ERR_PTR(-EINVAL);
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mux = kzalloc(sizeof(struct clk_mux2_scu), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_mux2_scu_ops;
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init.parent_names = parents;
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init.num_parents = num_parents;
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init.flags = flags |= CLK_SET_PARENT_NOCACHE;
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mux->hw.init = &init;
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mux->rsrc_id = rsrc_id;
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mux->clk_type = clk_type;
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clk = clk_register(NULL, &mux->hw);
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if (IS_ERR(clk))
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kfree(mux);
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return clk;
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}
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