394 lines
12 KiB
C
394 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MACH_IMX_CLK_H
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#define __MACH_IMX_CLK_H
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#include <linux/spinlock.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <soc/imx/src.h>
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extern spinlock_t imx_ccm_lock;
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void imx_check_clocks(struct clk *clks[], unsigned int count);
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void imx_register_uart_clocks(struct clk ** const clks[]);
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extern void imx_cscmr1_fixup(u32 *val);
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extern struct imx_sema4_mutex *amp_power_mutex;
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extern struct imx_shared_mem *shared_mem;
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extern bool uart_from_osc;
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extern const struct clk_ops clk_frac_divider_ops;
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enum imx_pllv1_type {
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IMX_PLLV1_IMX1,
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IMX_PLLV1_IMX21,
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IMX_PLLV1_IMX25,
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IMX_PLLV1_IMX27,
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IMX_PLLV1_IMX31,
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IMX_PLLV1_IMX35,
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};
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enum imx_int_pll_type {
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PLL_1416X,
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PLL_1443X,
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};
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enum imx_sccg_pll_type {
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SCCG_PLL1,
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SCCG_PLL2,
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};
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/* NOTE: Rate table should be kept sorted in descending order. */
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struct imx_int_pll_rate_table {
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unsigned int rate;
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unsigned int pdiv;
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unsigned int mdiv;
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unsigned int sdiv;
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unsigned int kdiv;
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};
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struct imx_int_pll_clk {
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enum imx_int_pll_type type;
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const struct imx_int_pll_rate_table *rate_table;
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int flags;
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};
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struct clk *imx_clk_int_pll(const char *name, const char *parent_name, void __iomem *base, const struct imx_int_pll_clk *pll_clk);
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struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
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const char *parent, void __iomem *base);
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struct clk *imx_clk_pllv2(const char *name, const char *parent,
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void __iomem *base);
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struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, void __iomem *base);
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struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, void __iomem *base, enum imx_sccg_pll_type pll_type);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_USB,
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IMX_PLLV3_USB_VF610,
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IMX_PLLV3_AV,
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IMX_PLLV3_ENET,
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IMX_PLLV3_ENET_IMX7,
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IMX_PLLV3_SYS_VF610,
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IMX_PLLV3_DDR_IMX7,
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IMX_PLLV3_AV_IMX7,
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IMX_PLLV3_PLL2,
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};
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/*
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* frac_divider, found on i.MX7ULP PCC module.
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* the output clock of the fractional divider is:
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* Divider output clock = Input clock * (FRAC + 1)
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* / (DIV + 1)
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*/
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struct clk_frac_divider {
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struct clk_hw hw;
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void __iomem *reg;
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u8 mshift;
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u8 mwidth;
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u32 mmask;
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u8 nshift;
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u8 nwidth;
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u32 nmask;
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};
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#define MAX_SHARED_CLK_NUMBER 100
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#define SHARED_MEM_MAGIC_NUMBER 0x12345678
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#define MCC_POWER_SHMEM_NUMBER (6)
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struct imx_shared_clk {
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struct clk *self;
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struct clk *parent;
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void *m4_clk;
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void *m4_clk_parent;
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u8 ca9_enabled;
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u8 cm4_enabled;
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};
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struct imx_shared_mem {
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u32 ca9_valid;
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u32 cm4_valid;
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struct imx_shared_clk imx_clk[MAX_SHARED_CLK_NUMBER];
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 div_mask);
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struct clk *imx_clk_pllv4(const char *name,
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const char *parent_name, void __iomem *base);
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struct clk *imx_clk_pllv5(const char *name, const char *parent_name,
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void __iomem *base);
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate_flags, spinlock_t *lock,
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unsigned int *share_count);
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struct clk * imx_obtain_fixed_clock(
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const char *name, unsigned long rate);
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struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u32 exclusive_mask);
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static inline void imx_clk_prepare_enable(struct clk *clk)
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{
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int ret = clk_prepare_enable(clk);
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if (ret)
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pr_err("failed to prepare and enable clk %s: %d\n",
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__clk_get_name(clk), ret);
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}
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static inline void imx_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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int ret = clk_set_parent(clk, parent);
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if (ret)
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pr_err("failed to set parent of clk %s to %s: %d\n",
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__clk_get_name(clk), __clk_get_name(parent), ret);
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}
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static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = clk_set_rate(clk, rate);
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if (ret)
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pr_err("failed to set rate of clk %s to %ld: %d\n",
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__clk_get_name(clk), rate, ret);
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}
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width,
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void __iomem *busy_reg, u8 busy_shift);
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struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
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u8 width, void __iomem *busy_reg, u8 busy_shift,
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const char **parent_names, int num_parents);
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struct clk *imx_clk_busy_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift);
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struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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void (*fixup)(u32 *val));
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struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents,
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int num_parents, void (*fixup)(u32 *val));
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static inline struct clk *imx_clk_fixed(const char *name, int rate)
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{
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return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
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}
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static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
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shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_fixed_factor(const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_register_fixed_factor(NULL, name, parent,
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CLK_SET_RATE_PARENT, mult, div);
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}
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static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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unsigned long flags)
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{
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return clk_register_divider(NULL, name, parent, flags,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, reg,
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shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
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void __iomem *reg, u8 shift, unsigned long flags)
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{
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return clk_register_gate2(NULL, name, parent, flags, reg,
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shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate2_shared(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, reg,
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shift, 0x3, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_shared2(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_cgr(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, cgr_val, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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/*
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* per design team's suggestion, clk root is NOT consuming
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* much power, and clk root enable/disable does NOT have domain
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* control, so they suggest to leave clk root always on when
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* M4 is enabled.
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*/
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if (imx_src_is_m4_enabled())
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return clk_register_fixed_factor(NULL, name, parent,
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CLK_SET_RATE_PARENT, 1, 1);
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else
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return clk_register_gate(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_mux_bus(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux_flags(const char *name,
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void __iomem *reg, u8 shift, u8 width, const char **parents,
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int num_parents, unsigned long flags)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux_flags_bus(const char *name,
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void __iomem *reg, u8 shift, u8 width, const char **paretns,
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int num_parents, unsigned long flags)
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{
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return clk_register_mux(NULL, name, paretns, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
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width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux_glitchless(const char *name,
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void __iomem *reg, u8 shift, u8 width, const char **parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT, reg, shift,
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width, 0, &imx_ccm_lock);
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}
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struct clk *imx_clk_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step);
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int imx_update_shared_mem(struct clk_hw *hw, bool enable);
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static inline int clk_on_imx6sx(void)
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{
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return of_machine_is_compatible("fsl,imx6sx");
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}
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struct clk *imx7ulp_clk_composite(const char *name, const char **parent_name,
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int num_parents, bool mux_present, bool rate_present,
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bool gate_present, void __iomem *reg);
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struct clk *imx_clk_pfdv2(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk *imx8m_clk_composite_flags(const char *name, const char **parent_names,
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int num_parents, void __iomem *reg, unsigned long flags);
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#define __imx8m_clk_composite(name, parent_names, reg, flags) \
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imx8m_clk_composite_flags(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, \
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flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define imx8m_clk_composite(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, 0)
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#define imx8m_clk_composite_critical(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
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#endif
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