347 lines
11 KiB
C
347 lines
11 KiB
C
/*
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* Copyright 2018 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IMX_HDP_CEC_H_
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#define _IMX_HDP_CEC_H_
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#include <linux/cec.h>
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#include "../hdp/util.h"
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#include "../hdp/address.h"
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/* regsiter define */
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/* register TX_MSG_HEADER */
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#define TX_MSG_HEADER 0
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#define F_TX_FOLLOWER_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_TX_FOLLOWER_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_TX_INITIATOR_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 4)
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#define F_TX_INITIATOR_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
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/* register TX_MSG_OPCODE */
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#define TX_MSG_OPCODE 1
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#define F_TX_MSG_OPCODE(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OPCODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP1 */
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#define TX_MSG_OP1 2
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#define F_TX_MSG_OP1(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP1_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP2 */
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#define TX_MSG_OP2 3
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#define F_TX_MSG_OP2(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP2_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP3 */
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#define TX_MSG_OP3 4
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#define F_TX_MSG_OP3(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP3_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP4 */
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#define TX_MSG_OP4 5
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#define F_TX_MSG_OP4(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP4_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP5 */
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#define TX_MSG_OP5 6
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#define F_TX_MSG_OP5(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP5_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP6 */
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#define TX_MSG_OP6 7
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#define F_TX_MSG_OP6(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP6_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP7 */
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#define TX_MSG_OP7 8
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#define F_TX_MSG_OP7(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP7_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP8 */
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#define TX_MSG_OP8 9
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#define F_TX_MSG_OP8(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP9 */
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#define TX_MSG_OP9 10
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#define F_TX_MSG_OP9(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP9_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP10 */
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#define TX_MSG_OP10 11
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#define F_TX_MSG_OP10(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP10_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP11 */
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#define TX_MSG_OP11 12
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#define F_TX_MSG_OP11(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP11_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP12 */
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#define TX_MSG_OP12 13
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#define F_TX_MSG_OP12(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP12_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP13 */
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#define TX_MSG_OP13 14
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#define F_TX_MSG_OP13(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP13_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_OP14 */
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#define TX_MSG_OP14 15
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#define F_TX_MSG_OP14(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_TX_MSG_OP14_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register TX_MSG_LENGTH */
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#define TX_MSG_LENGTH 16
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#define F_TX_MSG_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_TX_MSG_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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/* register TX_MSG_CMD */
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#define TX_MSG_CMD 17
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#define F_TX_MSG_CMD(x) (((x) & ((1 << 2) - 1)) << 0)
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#define F_TX_MSG_CMD_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
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/* register TX_WRITE_BUF */
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#define TX_WRITE_BUF 18
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#define F_TX_WRITE_BUF(x) (((x) & ((1 << 1) - 1)) << 0)
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#define F_TX_WRITE_BUF_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
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/* register TX_CLEAR_BUF */
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#define TX_CLEAR_BUF 19
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#define F_TX_CLEAR_BUF(x) (((x) & ((1 << 1) - 1)) << 0)
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#define F_TX_CLEAR_BUF_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
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/* register RX_MSG_CMD */
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#define RX_MSG_CMD 20
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#define F_RX_MSG_CMD(x) (((x) & ((1 << 2) - 1)) << 0)
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#define F_RX_MSG_CMD_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
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/* register RX_CLEAR_BUF */
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#define RX_CLEAR_BUF 21
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#define F_RX_CLEAR_BUF(x) (((x) & ((1 << 1) - 1)) << 0)
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#define F_RX_CLEAR_BUF_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
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/* register LOGICAL_ADDRESS_LA0 */
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#define LOGICAL_ADDRESS_LA0 22
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#define F_MY_LOG_ADDR0(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_MY_LOG_ADDR0_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_LOG_ADDR_VALID0(x) (((x) & ((1 << 1) - 1)) << 4)
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#define F_LOG_ADDR_VALID0_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
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/* register LOGICAL_ADDRESS_LA1 */
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#define LOGICAL_ADDRESS_LA1 23
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#define F_MY_LOG_ADDR1(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_MY_LOG_ADDR1_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_LOG_ADDR_VALID1(x) (((x) & ((1 << 1) - 1)) << 4)
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#define F_LOG_ADDR_VALID1_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
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/* register LOGICAL_ADDRESS_LA2 */
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#define LOGICAL_ADDRESS_LA2 24
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#define F_MY_LOG_ADDR2(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_MY_LOG_ADDR2_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_LOG_ADDR_VALID2(x) (((x) & ((1 << 1) - 1)) << 4)
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#define F_LOG_ADDR_VALID2_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
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/* register LOGICAL_ADDRESS_LA3 */
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#define LOGICAL_ADDRESS_LA3 25
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#define F_MY_LOG_ADDR3(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_MY_LOG_ADDR3_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_LOG_ADDR_VALID3(x) (((x) & ((1 << 1) - 1)) << 4)
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#define F_LOG_ADDR_VALID3_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
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/* register LOGICAL_ADDRESS_LA4 */
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#define LOGICAL_ADDRESS_LA4 26
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#define F_MY_LOG_ADDR4(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_MY_LOG_ADDR4_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_LOG_ADDR_VALID4(x) (((x) & ((1 << 1) - 1)) << 4)
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#define F_LOG_ADDR_VALID4_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
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/* register CLK_DIV_MSB */
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#define CLK_DIV_MSB 27
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#define F_CLK_DIV_MSB(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_CLK_DIV_MSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register CLK_DIV_LSB */
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#define CLK_DIV_LSB 28
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#define F_CLK_DIV_LSB(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_CLK_DIV_LSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register CDC_MSG */
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#define CDC_MSG 31
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#define F_CDC_MSG(x) (((x) & ((1 << 1) - 1)) << 0)
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#define F_CDC_MSG_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA1 */
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#define RX_MSG_DATA1 64
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#define F_RX_FOLLOWER_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_RX_FOLLOWER_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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#define F_RX_INITIATOR_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 4)
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#define F_RX_INITIATOR_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
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/* register RX_MSG_DATA2 */
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#define RX_MSG_DATA2 65
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#define F_RX_MSG_OPCODE(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OPCODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA3 */
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#define RX_MSG_DATA3 66
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#define F_RX_MSG_OP1(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP1_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA4 */
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#define RX_MSG_DATA4 67
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#define F_RX_MSG_OP2(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP2_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA5 */
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#define RX_MSG_DATA5 68
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#define F_RX_MSG_OP3(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP3_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA6 */
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#define RX_MSG_DATA6 69
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#define F_RX_MSG_OP4(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP4_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA7 */
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#define RX_MSG_DATA7 70
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#define F_RX_MSG_OP5(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP5_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA8 */
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#define RX_MSG_DATA8 71
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#define F_RX_MSG_OP6(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP6_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA9 */
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#define RX_MSG_DATA9 72
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#define F_RX_MSG_OP7(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP7_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA10 */
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#define RX_MSG_DATA10 73
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#define F_RX_MSG_OP8(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA11 */
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#define RX_MSG_DATA11 74
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#define F_RX_MSG_OP9(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP9_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA12 */
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#define RX_MSG_DATA12 75
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#define F_RX_MSG_OP10(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP10_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA13 */
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#define RX_MSG_DATA13 76
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#define F_RX_MSG_OP11(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP11_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA14 */
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#define RX_MSG_DATA14 77
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#define F_RX_MSG_OP12(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP12_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA15 */
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#define RX_MSG_DATA15 78
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#define F_RX_MSG_OP13(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP13_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_DATA16 */
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#define RX_MSG_DATA16 79
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#define F_RX_MSG_OP14(x) (((x) & ((1 << 8) - 1)) << 0)
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#define F_RX_MSG_OP14_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
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/* register RX_MSG_LENGTH */
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#define RX_MSG_LENGTH 80
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#define F_RX_MSG_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_RX_MSG_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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/* register RX_MSG_STATUS */
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#define RX_MSG_STATUS 81
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#define F_RX_MSG_STATUS(x) (((x) & ((1 << 2) - 1)) << 0)
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#define F_RX_MSG_STATUS_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
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/* register NUM_OF_MSG_RX_BUF */
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#define NUM_OF_MSG_RX_BUF 82
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#define F_RX_NUM_MSG(x) (((x) & ((1 << 4) - 1)) << 0)
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#define F_RX_NUM_MSG_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
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/* register TX_MSG_STATUS */
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#define TX_MSG_STATUS 83
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#define F_TX_MSG_STATUS(x) (((x) & ((1 << 2) - 1)) << 0)
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#define F_TX_MSG_STATUS_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
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/* register DB_L_TIMER */
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#define DB_L_TIMER 96
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/* register DB_M_TIMER */
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#define DB_M_TIMER 97
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/* register DB_H_TIMER */
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#define DB_H_TIMER 98
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#define RX_OP_TIMEOUT 10000
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#define TX_OP_TIMEOUT 10000
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/**
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* CEC Transceiver operation.
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*/
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enum {
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CEC_TX_STOP,
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CEC_TX_TRANSMIT,
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CEC_TX_ABORT,
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CEC_TX_ABORT_AND_TRANSMIT
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};
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/**
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* CEC Transceiver status.
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*/
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enum {
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CEC_STS_IDLE,
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CEC_STS_BUSY,
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CEC_STS_SUCCESS,
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CEC_STS_ERROR
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};
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/**
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* CEC Receiver operation.
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*/
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enum {
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CEC_RX_STOP,
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CEC_RX_READ,
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CEC_RX_DISABLE,
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CEC_RX_ABORT_AND_CLR_FIFO
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};
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struct imx_cec_dev {
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struct cec_adapter *adap;
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struct device *dev;
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struct mutex lock;
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struct cec_msg msg;
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u32 clk_div;
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struct task_struct *cec_worker;
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/* inited by HDP controller driver */
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struct hdp_mem *mem;
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struct hdp_rw_func *rw;
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};
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int imx_cec_register(struct imx_cec_dev *cec);
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int imx_cec_unregister(struct imx_cec_dev *cec);
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#endif
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