532 lines
14 KiB
C
532 lines
14 KiB
C
/*
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* Copyright 2017 NXP
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/perf_event.h>
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#include <linux/slab.h>
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#define COUNTER_CNTL 0x0
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#define COUNTER_READ 0x20
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#define COUNTER_DPCR1 0x30
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#define CNTL_OVER 0x1
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#define CNTL_CLEAR 0x2
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#define CNTL_EN 0x4
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#define CNTL_EN_MASK 0xFFFFFFFB
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#define CNTL_CLEAR_MASK 0xFFFFFFFD
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#define CNTL_OVER_MASK 0xFFFFFFFE
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#define CNTL_CSV_SHIFT 24
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#define CNTL_CSV_MASK (0xFF << CNTL_CSV_SHIFT)
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#define EVENT_CYCLES_ID 0
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#define EVENT_CYCLES_COUNTER 0
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#define NUM_COUNTER 4
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#define MAX_EVENT 3
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#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
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#define DDR_PERF_DEV_NAME "ddr_perf"
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static DEFINE_IDA(ddr_ida);
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PMU_EVENT_ATTR_STRING(cycles, ddr_perf_cycles, "event=0x00");
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PMU_EVENT_ATTR_STRING(selfresh, ddr_perf_selfresh, "event=0x01");
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PMU_EVENT_ATTR_STRING(read-access, ddr_perf_read_accesses, "event=0x04");
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PMU_EVENT_ATTR_STRING(write-access, ddr_perf_write_accesses, "event=0x05");
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PMU_EVENT_ATTR_STRING(read-queue-depth, ddr_perf_read_queue_depth,
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"event=0x08");
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PMU_EVENT_ATTR_STRING(write-queue-depth, ddr_perf_write_queue_depth,
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"event=0x09");
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PMU_EVENT_ATTR_STRING(lp-read-credit-cnt, ddr_perf_lp_read_credit_cnt,
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"event=0x10");
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PMU_EVENT_ATTR_STRING(hp-read-credit-cnt, ddr_perf_hp_read_credit_cnt,
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"event=0x11");
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PMU_EVENT_ATTR_STRING(write-credit-cnt, ddr_perf_write_credit_cnt,
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"event=0x12");
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PMU_EVENT_ATTR_STRING(read-command, ddr_perf_read_command, "event=0x20");
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PMU_EVENT_ATTR_STRING(write-command, ddr_perf_write_command, "event=0x21");
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PMU_EVENT_ATTR_STRING(read-modify-write-command,
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ddr_perf_read_modify_write_command, "event=0x22");
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PMU_EVENT_ATTR_STRING(hp-read, ddr_perf_hp_read, "event=0x23");
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PMU_EVENT_ATTR_STRING(hp-req-nodcredit, ddr_perf_hp_req_nocredit, "event=0x24");
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PMU_EVENT_ATTR_STRING(hp-xact-credit, ddr_perf_hp_xact_credit, "event=0x25");
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PMU_EVENT_ATTR_STRING(lp-req-nocredit, ddr_perf_lp_req_nocredit, "event=0x26");
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PMU_EVENT_ATTR_STRING(lp-xact-credit, ddr_perf_lp_xact_credit, "event=0x27");
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PMU_EVENT_ATTR_STRING(wr-xact-credit, ddr_perf_wr_xact_credit, "event=0x29");
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PMU_EVENT_ATTR_STRING(read-cycles, ddr_perf_read_cycles, "event=0x2a");
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PMU_EVENT_ATTR_STRING(write-cycles, ddr_perf_write_cycles, "event=0x2b");
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PMU_EVENT_ATTR_STRING(read-write-transition, ddr_perf_read_write_transition,
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"event=0x30");
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PMU_EVENT_ATTR_STRING(precharge, ddr_perf_precharge, "event=0x31");
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PMU_EVENT_ATTR_STRING(activate, ddr_perf_activate, "event=0x32");
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PMU_EVENT_ATTR_STRING(load-mode, ddr_perf_load_mode, "event=0x33");
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PMU_EVENT_ATTR_STRING(mwr, ddr_perf_mwr, "event=0x34");
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PMU_EVENT_ATTR_STRING(read, ddr_perf_read, "event=0x35");
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PMU_EVENT_ATTR_STRING(read-activate, ddr_perf_read_activate, "event=0x36");
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PMU_EVENT_ATTR_STRING(refresh, ddr_perf_refresh, "event=0x37");
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PMU_EVENT_ATTR_STRING(write, ddr_perf_write, "event=0x38");
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PMU_EVENT_ATTR_STRING(raw-hazard, ddr_perf_raw_hazard, "event=0x39");
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PMU_EVENT_ATTR_STRING(axid-read, ddr_perf_axid_read, "event=0x41");
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PMU_EVENT_ATTR_STRING(axid-write, ddr_perf_axid_write, "event=0x42");
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#define DDR_CAP_AXI_ID 0x1
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struct fsl_ddr_devtype_data {
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unsigned int flags;
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};
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static const struct fsl_ddr_devtype_data imx8_data;
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static const struct fsl_ddr_devtype_data imx8m_data = {
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.flags = DDR_CAP_AXI_ID,
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};
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static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
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{ .compatible = "fsl,imx8-ddr-pmu", .data = (void*)&imx8_data},
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{ .compatible = "fsl,imx8m-ddr-pmu", .data = (void*)&imx8m_data},
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{ /* sentinel */ }
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};
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struct ddr_pmu {
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struct pmu pmu;
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void __iomem *base;
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cpumask_t cpu;
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struct hlist_node node;
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struct device *dev;
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struct perf_event *active_events[NUM_COUNTER];
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int total_events;
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bool cycles_active;
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struct fsl_ddr_devtype_data *devtype;
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};
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static ssize_t ddr_perf_cpumask_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct ddr_pmu *pmu = dev_get_drvdata(dev);
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return cpumap_print_to_pagebuf(true, buf, &pmu->cpu);
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}
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static struct device_attribute ddr_perf_cpumask_attr =
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__ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
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static struct attribute *ddr_perf_cpumask_attrs[] = {
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&ddr_perf_cpumask_attr.attr,
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NULL,
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};
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static struct attribute_group ddr_perf_cpumask_attr_group = {
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.attrs = ddr_perf_cpumask_attrs,
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};
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static struct attribute *ddr_perf_events_attrs[] = {
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&ddr_perf_cycles.attr.attr,
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&ddr_perf_selfresh.attr.attr,
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&ddr_perf_read_accesses.attr.attr,
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&ddr_perf_write_accesses.attr.attr,
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&ddr_perf_read_queue_depth.attr.attr,
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&ddr_perf_write_queue_depth.attr.attr,
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&ddr_perf_lp_read_credit_cnt.attr.attr,
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&ddr_perf_hp_read_credit_cnt.attr.attr,
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&ddr_perf_write_credit_cnt.attr.attr,
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&ddr_perf_read_command.attr.attr,
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&ddr_perf_write_command.attr.attr,
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&ddr_perf_read_modify_write_command.attr.attr,
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&ddr_perf_hp_read.attr.attr,
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&ddr_perf_hp_req_nocredit.attr.attr,
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&ddr_perf_hp_xact_credit.attr.attr,
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&ddr_perf_lp_req_nocredit.attr.attr,
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&ddr_perf_lp_xact_credit.attr.attr,
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&ddr_perf_wr_xact_credit.attr.attr,
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&ddr_perf_read_cycles.attr.attr,
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&ddr_perf_write_cycles.attr.attr,
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&ddr_perf_read_write_transition.attr.attr,
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&ddr_perf_precharge.attr.attr,
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&ddr_perf_activate.attr.attr,
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&ddr_perf_load_mode.attr.attr,
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&ddr_perf_mwr.attr.attr,
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&ddr_perf_read.attr.attr,
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&ddr_perf_read_activate.attr.attr,
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&ddr_perf_refresh.attr.attr,
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&ddr_perf_write.attr.attr,
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&ddr_perf_raw_hazard.attr.attr,
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&ddr_perf_axid_read.attr.attr,
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&ddr_perf_axid_write.attr.attr,
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NULL,
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};
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static struct attribute_group ddr_perf_events_attr_group = {
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.name = "events",
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.attrs = ddr_perf_events_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-63");
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PMU_FORMAT_ATTR(axi_id, "config1:0-63");
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static struct attribute *ddr_perf_format_attrs[] = {
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&format_attr_event.attr,
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&format_attr_axi_id.attr,
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NULL,
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};
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static struct attribute_group ddr_perf_format_attr_group = {
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.name = "format",
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.attrs = ddr_perf_format_attrs,
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};
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static const struct attribute_group *attr_groups[] = {
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&ddr_perf_events_attr_group,
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&ddr_perf_format_attr_group,
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&ddr_perf_cpumask_attr_group,
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NULL,
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};
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static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
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{
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int i;
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/* Always map cycle event to counter 0 */
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if (event == EVENT_CYCLES_ID)
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return EVENT_CYCLES_COUNTER;
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for (i = 1; i < NUM_COUNTER; i++)
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if (pmu->active_events[i] == NULL)
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return i;
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return -ENOENT;
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}
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static u32 ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
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{
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if (counter < 0 || counter >= NUM_COUNTER)
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return -ENOENT;
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pmu->active_events[counter] = NULL;
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return 0;
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}
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static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
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{
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return readl(pmu->base + COUNTER_READ + counter * 4);
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}
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static int ddr_perf_event_init(struct perf_event *event)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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return -EOPNOTSUPP;
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if (event->cpu < 0) {
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dev_warn(pmu->dev, "Can't provide per-task data!\n");
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return -EOPNOTSUPP;
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}
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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event->attr.sample_period)
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return -EINVAL;
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event->cpu = cpumask_first(&pmu->cpu);
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hwc->idx = -1;
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return 0;
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}
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static void ddr_perf_event_update(struct perf_event *event)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u64 delta, prev_raw_count, new_raw_count;
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int counter = hwc->idx;
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do {
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = ddr_perf_read_counter(pmu, counter);
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} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count);
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delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
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local64_add(delta, &event->count);
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}
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static void ddr_perf_event_enable(struct ddr_pmu *pmu, int config,
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int counter, bool enable)
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{
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u8 reg = counter * 4 + COUNTER_CNTL;
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int val;
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if (enable) {
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/* Clear counter, then enable it. */
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writel(0, pmu->base + reg);
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val = CNTL_EN | CNTL_CLEAR;
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val |= (config << CNTL_CSV_SHIFT) & CNTL_CSV_MASK;
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} else {
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/* Disable counter */
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val = readl(pmu->base + reg) & CNTL_EN_MASK;
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}
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writel(val, pmu->base + reg);
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if (config == EVENT_CYCLES_ID)
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pmu->cycles_active = enable;
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}
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static void ddr_perf_event_start(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter = hwc->idx;
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if (pmu->devtype->flags & DDR_CAP_AXI_ID) {
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if (event->attr.config == 0x41 ||
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event->attr.config == 0x42) {
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int val = event->attr.config1;
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writel(val, pmu->base + COUNTER_DPCR1);
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}
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}
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local64_set(&hwc->prev_count, 0);
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ddr_perf_event_enable(pmu, event->attr.config, counter, true);
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/*
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* If the cycles counter wasn't explicitly selected,
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* we will enable it now.
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*/
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if (counter > 0 && !pmu->cycles_active)
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ddr_perf_event_enable(pmu, EVENT_CYCLES_ID,
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EVENT_CYCLES_COUNTER, true);
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}
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static int ddr_perf_event_add(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter;
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int cfg = event->attr.config;
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counter = ddr_perf_alloc_counter(pmu, cfg);
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if (counter < 0) {
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dev_warn(pmu->dev, "There are not enough counters\n");
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return -EOPNOTSUPP;
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}
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pmu->active_events[counter] = event;
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pmu->total_events++;
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hwc->idx = counter;
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if (flags & PERF_EF_START)
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ddr_perf_event_start(event, flags);
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local64_set(&hwc->prev_count, ddr_perf_read_counter(pmu, counter));
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return 0;
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}
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static void ddr_perf_event_stop(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter = hwc->idx;
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ddr_perf_event_enable(pmu, event->attr.config, counter, false);
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ddr_perf_event_update(event);
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}
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static void ddr_perf_event_del(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter = hwc->idx;
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ddr_perf_event_stop(event, PERF_EF_UPDATE);
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ddr_perf_free_counter(pmu, counter);
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pmu->total_events--;
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hwc->idx = -1;
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/* If all events have stopped, stop the cycles counter as well */
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if ((pmu->total_events == 0) && pmu->cycles_active)
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ddr_perf_event_enable(pmu, EVENT_CYCLES_ID,
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EVENT_CYCLES_COUNTER, false);
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}
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static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
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struct device *dev)
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{
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*pmu = (struct ddr_pmu) {
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.pmu = (struct pmu) {
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.task_ctx_nr = perf_invalid_context,
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.attr_groups = attr_groups,
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.event_init = ddr_perf_event_init,
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.add = ddr_perf_event_add,
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.del = ddr_perf_event_del,
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.start = ddr_perf_event_start,
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.stop = ddr_perf_event_stop,
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.read = ddr_perf_event_update,
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},
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.base = base,
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.dev = dev,
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};
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return ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
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}
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static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
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{
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int i;
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u8 reg;
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int val;
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int counter;
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struct ddr_pmu *pmu = (struct ddr_pmu *) p;
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struct perf_event *event;
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/*
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* The cycles counter has overflowed. Update all of the local counter
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* values, then reset the cycles counter, so the others can continue
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* counting.
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*/
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for (i = 0; i <= pmu->total_events; i++) {
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if (pmu->active_events[i] != NULL) {
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event = pmu->active_events[i];
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counter = event->hw.idx;
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reg = counter * 4 + COUNTER_CNTL;
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val = readl(pmu->base + reg);
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ddr_perf_event_update(event);
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if (val & CNTL_OVER) {
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/* Clear counter, then re-enable it. */
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ddr_perf_event_enable(pmu, event->attr.config,
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counter, true);
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/* Update event again to reset prev_count */
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ddr_perf_event_update(event);
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}
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}
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}
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/*
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* Reset the cycles counter regardless if it was explicitly
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* enabled or not.
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*/
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ddr_perf_event_enable(pmu, EVENT_CYCLES_ID,
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EVENT_CYCLES_COUNTER, true);
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return IRQ_HANDLED;
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}
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static int ddr_perf_probe(struct platform_device *pdev)
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{
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struct ddr_pmu *pmu;
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struct device_node *np;
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void __iomem *base;
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struct resource *iomem;
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char *name;
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int num;
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int ret;
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u32 irq;
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const struct of_device_id *of_id =
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of_match_device(imx_ddr_pmu_dt_ids, &pdev->dev);
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iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, iomem);
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if (IS_ERR(base)) {
|
|
ret = PTR_ERR(base);
|
|
return ret;
|
|
}
|
|
|
|
np = pdev->dev.of_node;
|
|
|
|
pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
|
|
if (!pmu)
|
|
return -ENOMEM;
|
|
|
|
num = ddr_perf_init(pmu, base, &pdev->dev);
|
|
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ddr%d", num);
|
|
|
|
pmu->devtype = (struct fsl_ddr_devtype_data *)of_id->data;
|
|
|
|
cpumask_set_cpu(smp_processor_id(), &pmu->cpu);
|
|
ret = perf_pmu_register(&(pmu->pmu), name, -1);
|
|
if (ret)
|
|
goto ddr_perf_err;
|
|
|
|
/* Request irq */
|
|
irq = of_irq_get(np, 0);
|
|
if (irq < 0) {
|
|
pr_err("Failed to get irq: %d", irq);
|
|
goto ddr_perf_err;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, irq,
|
|
ddr_perf_irq_handler, NULL,
|
|
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
|
|
DDR_PERF_DEV_NAME,
|
|
pmu);
|
|
if (ret < 0) {
|
|
pr_err("Request irq failed: %d", ret);
|
|
goto ddr_perf_irq_err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
ddr_perf_irq_err:
|
|
perf_pmu_unregister(&(pmu->pmu));
|
|
ddr_perf_err:
|
|
pr_warn("i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
|
|
kfree(pmu);
|
|
return ret;
|
|
}
|
|
|
|
|
|
static int ddr_perf_remove(struct platform_device *pdev)
|
|
{
|
|
struct ddr_pmu *pmu = platform_get_drvdata(pdev);
|
|
|
|
perf_pmu_unregister(&pmu->pmu);
|
|
kfree(pmu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver imx_ddr_pmu_driver = {
|
|
.driver = {
|
|
.name = "imx-ddr-pmu",
|
|
.of_match_table = imx_ddr_pmu_dt_ids,
|
|
},
|
|
.probe = ddr_perf_probe,
|
|
.remove = ddr_perf_remove,
|
|
};
|
|
|
|
static int __init imx_ddr_pmu_init(void)
|
|
{
|
|
return platform_driver_register(&imx_ddr_pmu_driver);
|
|
}
|
|
|
|
module_init(imx_ddr_pmu_init);
|
|
|