539 lines
13 KiB
C
539 lines
13 KiB
C
/*
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* Copyright 2018 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy-mixel-mipi-dsi.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <soc/imx8/sc/sci.h>
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#define DPHY_PD_DPHY 0x00
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#define DPHY_M_PRG_HS_PREPARE 0x04
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#define DPHY_MC_PRG_HS_PREPARE 0x08
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#define DPHY_M_PRG_HS_ZERO 0x0c
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#define DPHY_MC_PRG_HS_ZERO 0x10
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#define DPHY_M_PRG_HS_TRAIL 0x14
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#define DPHY_MC_PRG_HS_TRAIL 0x18
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#define DPHY_PD_PLL 0x1c
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#define DPHY_TST 0x20
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#define DPHY_CN 0x24
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#define DPHY_CM 0x28
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#define DPHY_CO 0x2c
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#define DPHY_LOCK 0x30
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#define DPHY_LOCK_BYP 0x34
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#define MBPS(x) ((x) * 1000000)
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#define DATA_RATE_MAX_SPEED MBPS(1500)
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#define DATA_RATE_MIN_SPEED MBPS(80)
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#define CN_BUF 0xcb7a89c0
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#define CO_BUF 0x63
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#define CM(x) ( \
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((x) < 32)?0xe0|((x)-16) : \
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((x) < 64)?0xc0|((x)-32) : \
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((x) < 128)?0x80|((x)-64) : \
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((x) - 128))
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#define CN(x) (((x) == 1)?0x1f : (((CN_BUF)>>((x)-1))&0x1f))
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#define CO(x) ((CO_BUF)>>(8-(x))&0x3)
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/* PHY power on is LOW_ENABLE */
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#define PWR_ON 0
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#define PWR_OFF 1
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struct pll_divider {
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u32 cm;
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u32 cn;
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u32 co;
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};
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struct devtype {
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bool have_sc;
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u8 reg_tx_rcal;
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u8 reg_auto_pd_en;
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u8 reg_rxlprp;
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u8 reg_rxcdrp;
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u8 reg_rxhs_settle;
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u8 reg_bypass_pll;
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};
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struct mixel_mipi_phy_priv {
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struct device *dev;
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void __iomem *base;
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const struct devtype *plat_data;
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sc_rsrc_t mipi_id;
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struct pll_divider divider;
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struct mutex lock;
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unsigned long data_rate;
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};
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static inline u32 phy_read(struct phy *phy, unsigned int reg)
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{
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struct mixel_mipi_phy_priv *priv = phy_get_drvdata(phy);
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return readl(priv->base + reg);
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}
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static inline void phy_write(struct phy *phy, u32 value, unsigned int reg)
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{
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struct mixel_mipi_phy_priv *priv = phy_get_drvdata(phy);
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writel(value, priv->base + reg);
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}
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/*
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* mixel_phy_mipi_set_phy_speed:
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* Input params:
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* bit_clk: PHY PLL needed output clock
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* ref_clk: reference input clock for the PHY PLL
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*
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* Returns:
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* 0: if the bit_clk can be achieved for the given ref_clk
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* -EINVAL: otherwise
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*/
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int mixel_phy_mipi_set_phy_speed(struct phy *phy,
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unsigned long bit_clk,
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unsigned long ref_clk,
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bool best_match)
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{
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struct mixel_mipi_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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u32 div_rate;
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u32 numerator = 0;
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u32 denominator = 1;
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if (bit_clk > DATA_RATE_MAX_SPEED || bit_clk < DATA_RATE_MIN_SPEED)
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return -EINVAL;
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/* simulated fixed point with 3 decimals */
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div_rate = (bit_clk * 1000) / ref_clk;
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while (denominator <= 256) {
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if (div_rate % 1000 == 0)
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numerator = div_rate / 1000;
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if (numerator > 15)
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break;
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denominator = denominator << 1;
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div_rate = div_rate << 1;
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}
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/* CM ranges between 16 and 255 */
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/* CN ranges between 1 and 32 */
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/* CO is power of 2: 1, 2, 4, 8 */
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if (best_match && numerator < 16)
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numerator = div_rate / 1000;
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if (best_match && numerator > 255) {
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while (numerator > 255 && denominator > 1) {
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numerator = DIV_ROUND_UP(numerator, 2);
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denominator = denominator >> 1;
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}
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}
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if (numerator < 16 || numerator > 255)
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return -EINVAL;
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if (best_match)
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numerator = DIV_ROUND_UP(numerator, denominator) * denominator;
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priv->divider.cn = 1;
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if (denominator > 8) {
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priv->divider.cn = denominator >> 3;
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denominator = 8;
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}
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priv->divider.co = denominator;
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priv->divider.cm = numerator;
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priv->data_rate = bit_clk;
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return 0;
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}
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EXPORT_SYMBOL_GPL(mixel_phy_mipi_set_phy_speed);
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static int mixel_mipi_phy_enable(struct phy *phy, u32 reset)
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{
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struct mixel_mipi_phy_priv *priv = phy_get_drvdata(phy);
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sc_err_t sci_err = 0;
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sc_ipc_t ipc_handle = 0;
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u32 mu_id;
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sci_err = sc_ipc_getMuID(&mu_id);
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if (sci_err != SC_ERR_NONE) {
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dev_err(&phy->dev, "Failed to get MU ID (%d)\n", sci_err);
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return -ENODEV;
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}
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sci_err = sc_ipc_open(&ipc_handle, mu_id);
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if (sci_err != SC_ERR_NONE) {
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dev_err(&phy->dev, "Failed to open IPC (%d)\n", sci_err);
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return -ENODEV;
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}
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sci_err = sc_misc_set_control(ipc_handle,
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priv->mipi_id,
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SC_C_PHY_RESET,
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reset);
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if (sci_err != SC_ERR_NONE) {
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dev_err(&phy->dev, "Failed to reset DPHY (%d)\n", sci_err);
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sc_ipc_close(ipc_handle);
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return -ENODEV;
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}
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sc_ipc_close(ipc_handle);
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return 0;
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}
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/*
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* We tried our best here to use the values as specified in
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* Reference Manual, but we got unstable results. So, these values
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* are hacked from their original explanation as found in RM.
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*/
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static void mixel_phy_set_prg_regs(struct phy *phy)
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{
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struct mixel_mipi_phy_priv *priv = phy_get_drvdata(phy);
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unsigned int hs_reg;
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/* MC_PRG_HS_PREPARE = 1.0 * Ttxescape if DPHY_MC_PRG_HS_PREPARE = 0
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*
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* MC_PRG_HS_PREPARE = 1.5 * Ttxescape if DPHY_MC_PRG_HS_PREPARE = 1
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*
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* Assume Ftxescape is 18-20 MHz with DPHY_MC_PRG_HS_PREPARE = 0,
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* this gives 55-50 ns.
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* The specification is 38 to 95 ns.
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*/
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phy_write(phy, 0x00, DPHY_MC_PRG_HS_PREPARE);
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/* PRG_HS_PREPARE
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* for PRG_HS_PREPARE = 00, THS-PREPARE = 1 * TxClkEsc Period
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* PRG_HS_PREPARE = 01, THS-PREPARE = 1.5 * TxClkEsc Period
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* PRG_HS_PREPARE = 10, THS-PREPARE = 2 * TxClkEsc Period
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* PRG_HS_PREPARE = 11, THS-PREPARE = 2.5 * TxClkEsc Period
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*
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* The specification for THS-PREPARE is
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* Min (40ns + 4*UI)
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* Max 85ns +6*UI
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*/
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if (priv->data_rate <= MBPS(61))
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phy_write(phy, 0x03, DPHY_M_PRG_HS_PREPARE);
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else if (priv->data_rate <= MBPS(90))
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phy_write(phy, 0x02, DPHY_M_PRG_HS_PREPARE);
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else if (priv->data_rate <= MBPS(500))
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phy_write(phy, 0x01, DPHY_M_PRG_HS_PREPARE);
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else
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phy_write(phy, 0x00, DPHY_M_PRG_HS_PREPARE);
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/* MC_PRG_HS_ZERO
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*
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* T-CLK-ZERO = ( MC_PRG_HS_ZERO + 3) * (TxByteClkHS Period)
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*
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* The minimum specification for THS-PREPARE is 262 ns.
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*
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*/
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hs_reg =
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/* simplified equation y = .034x - 2.5
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*
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* This a linear interpolation of the values from the
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* PHY user guide
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*/
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(34 * (priv->data_rate/1000000) - 2500) / 1000;
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if (hs_reg < 1)
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hs_reg = 1;
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phy_write(phy, hs_reg, DPHY_MC_PRG_HS_ZERO);
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/* M_PRG_HS_ZERO
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*
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* TT-HS-ZERO =(M_PRG_HS_ZERO + 6) * (TxByteClkHS Period)
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*
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* The minimum specification for THS-ZERO 105ns + 6*UI.
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*
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*/
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hs_reg =
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/* simplified equation y = .0144x - 4.75
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*
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* This a linear interpolation of the values from the
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* PHY user guide
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*/
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(144 * (priv->data_rate/1000000) - 47500) / 10000;
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if (hs_reg < 1)
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hs_reg = 1;
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phy_write(phy, hs_reg, DPHY_M_PRG_HS_ZERO);
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/* MC_PRG_HS_TRAIL and M_PRG_HS_TRAIL
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*
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* THS-TRAIL =(PRG_HS_TRAIL) * (TxByteClkHS Period)
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*
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* The specification for THS-TRAIL is
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* Min (60ns + 4*UI)
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* Typical (82.5ns + 8*UI)
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* Max (105ns + 12*UI)
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*
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*/
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hs_reg =
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/* simplified equation y = .0103x + 1
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*
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* This a linear interpolation of the values from the
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* PHY user guide
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*/
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(103 * (priv->data_rate/1000000) + 10000) / 10000;
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if (hs_reg > 15)
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hs_reg = 15;
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if (hs_reg < 1)
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hs_reg = 1;
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phy_write(phy, hs_reg, DPHY_MC_PRG_HS_TRAIL);
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phy_write(phy, hs_reg, DPHY_M_PRG_HS_TRAIL);
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/* M_PRG_RXHS_SETTLE */
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if (priv->plat_data->reg_rxhs_settle == 0xFF)
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return;
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if (priv->data_rate < MBPS(80))
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phy_write(phy, 0x0d, priv->plat_data->reg_rxhs_settle);
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else if (priv->data_rate < MBPS(90))
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phy_write(phy, 0x0c, priv->plat_data->reg_rxhs_settle);
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else if (priv->data_rate < MBPS(125))
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phy_write(phy, 0x0b, priv->plat_data->reg_rxhs_settle);
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else if (priv->data_rate < MBPS(150))
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phy_write(phy, 0x0a, priv->plat_data->reg_rxhs_settle);
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else if (priv->data_rate < MBPS(225))
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phy_write(phy, 0x09, priv->plat_data->reg_rxhs_settle);
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else if (priv->data_rate < MBPS(500))
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phy_write(phy, 0x08, priv->plat_data->reg_rxhs_settle);
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else
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phy_write(phy, 0x07, priv->plat_data->reg_rxhs_settle);
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}
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static int mixel_mipi_phy_init(struct phy *phy)
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{
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struct mixel_mipi_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
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mutex_lock(&priv->lock);
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phy_write(phy, PWR_OFF, DPHY_PD_PLL);
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phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
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mixel_phy_set_prg_regs(phy);
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phy_write(phy, 0x00, DPHY_LOCK_BYP);
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if (priv->plat_data->reg_tx_rcal != 0xFF)
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phy_write(phy, 0x01, priv->plat_data->reg_tx_rcal);
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if (priv->plat_data->reg_auto_pd_en != 0xFF)
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phy_write(phy, 0x00, priv->plat_data->reg_auto_pd_en);
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if (priv->plat_data->reg_rxlprp != 0xFF)
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phy_write(phy, 0x02, priv->plat_data->reg_rxlprp);
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if (priv->plat_data->reg_rxcdrp != 0xFF)
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phy_write(phy, 0x02, priv->plat_data->reg_rxcdrp);
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phy_write(phy, 0x25, DPHY_TST);
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/* VCO = REF_CLK * CM / CN * CO */
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if (priv->divider.cm < 16 || priv->divider.cm > 255 ||
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priv->divider.cn < 1 || priv->divider.cn > 32 ||
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priv->divider.co < 1 || priv->divider.co > 8) {
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dev_err(&phy->dev, "Invalid CM/CN/CO values! (%u/%u/%u)\n",
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priv->divider.cm, priv->divider.cn, priv->divider.co);
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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dev_dbg(&phy->dev, "Using CM:%u CN:%u CO:%u\n",
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priv->divider.cm, priv->divider.cn, priv->divider.co);
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phy_write(phy, CM(priv->divider.cm), DPHY_CM);
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phy_write(phy, CN(priv->divider.cn), DPHY_CN);
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phy_write(phy, CO(priv->divider.co), DPHY_CO);
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mutex_unlock(&priv->lock);
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return 0;
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}
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static int mixel_mipi_phy_exit(struct phy *phy)
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{
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phy_write(phy, 0, DPHY_CM);
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phy_write(phy, 0, DPHY_CN);
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phy_write(phy, 0, DPHY_CO);
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return 0;
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}
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static int mixel_mipi_phy_power_on(struct phy *phy)
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{
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struct mixel_mipi_phy_priv *priv = phy_get_drvdata(phy);
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u32 lock, timeout;
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int ret = 0;
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mutex_lock(&priv->lock);
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phy_write(phy, PWR_ON, DPHY_PD_PLL);
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timeout = 100;
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while (!(lock = phy_read(phy, DPHY_LOCK))) {
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udelay(10);
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if (--timeout == 0) {
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dev_err(&phy->dev, "Could not get DPHY lock!\n");
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phy_write(phy, PWR_OFF, DPHY_PD_PLL);
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mutex_unlock(&priv->lock);
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return -EINVAL;
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}
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}
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dev_dbg(&phy->dev, "DPHY lock acquired after %d tries\n",
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(100 - timeout));
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phy_write(phy, PWR_ON, DPHY_PD_DPHY);
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if (priv->plat_data->have_sc)
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ret = mixel_mipi_phy_enable(phy, 1);
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mutex_unlock(&priv->lock);
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return ret;
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}
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static int mixel_mipi_phy_power_off(struct phy *phy)
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{
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struct mixel_mipi_phy_priv *priv = phy_get_drvdata(phy);
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int ret = 0;
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mutex_lock(&priv->lock);
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phy_write(phy, PWR_OFF, DPHY_PD_PLL);
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phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
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if (priv->plat_data->have_sc)
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ret = mixel_mipi_phy_enable(phy, 0);
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mutex_unlock(&priv->lock);
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return ret;
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}
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static const struct phy_ops mixel_mipi_phy_ops = {
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.init = mixel_mipi_phy_init,
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.exit = mixel_mipi_phy_exit,
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.power_on = mixel_mipi_phy_power_on,
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.power_off = mixel_mipi_phy_power_off,
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.owner = THIS_MODULE,
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};
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static struct devtype imx8qm_dev = {
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.have_sc = true,
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.reg_tx_rcal = 0xFF,
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.reg_auto_pd_en = 0x38,
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.reg_rxlprp = 0x3c,
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.reg_rxcdrp = 0x40,
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.reg_rxhs_settle = 0x44,
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.reg_bypass_pll = 0xFF,
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};
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static struct devtype imx8qxp_dev = {
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.have_sc = true,
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.reg_tx_rcal = 0xFF,
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.reg_auto_pd_en = 0x38,
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.reg_rxlprp = 0x3c,
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.reg_rxcdrp = 0x40,
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.reg_rxhs_settle = 0x44,
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.reg_bypass_pll = 0xFF,
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};
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static struct devtype imx8mq_dev = {
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.have_sc = false,
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.reg_tx_rcal = 0x38,
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.reg_auto_pd_en = 0x3c,
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.reg_rxlprp = 0x40,
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.reg_rxcdrp = 0x44,
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.reg_rxhs_settle = 0x48,
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.reg_bypass_pll = 0x4c,
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};
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static const struct of_device_id mixel_mipi_phy_of_match[] = {
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{ .compatible = "mixel,imx8qm-mipi-dsi-phy", .data = &imx8qm_dev },
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{ .compatible = "mixel,imx8qxp-mipi-dsi-phy", .data = &imx8qxp_dev },
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{ .compatible = "mixel,imx8mq-mipi-dsi-phy", .data = &imx8mq_dev },
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{}
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};
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MODULE_DEVICE_TABLE(of, mixel_mipi_phy_of_match);
|
|
|
|
static int mixel_mipi_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
const struct of_device_id *of_id =
|
|
of_match_device(mixel_mipi_phy_of_match, dev);
|
|
struct phy_provider *phy_provider;
|
|
struct mixel_mipi_phy_priv *priv;
|
|
struct resource *res;
|
|
struct phy *phy;
|
|
int phy_id = 0;
|
|
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
priv->base = devm_ioremap(dev, res->start, SZ_256);
|
|
if (IS_ERR(priv->base))
|
|
return PTR_ERR(priv->base);
|
|
|
|
priv->plat_data = of_id->data;
|
|
|
|
phy_id = of_alias_get_id(np, "dsi_phy");
|
|
if (phy_id < 0) {
|
|
dev_err(dev, "No dsi_phy alias found!");
|
|
return phy_id;
|
|
}
|
|
|
|
priv->mipi_id = phy_id?SC_R_MIPI_1:SC_R_MIPI_0;
|
|
|
|
priv->dev = dev;
|
|
|
|
mutex_init(&priv->lock);
|
|
dev_set_drvdata(dev, priv);
|
|
|
|
phy = devm_phy_create(dev, np, &mixel_mipi_phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(dev, "Failed to create phy\n");
|
|
return PTR_ERR(phy);
|
|
}
|
|
phy_set_drvdata(phy, priv);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static struct platform_driver mixel_mipi_phy_driver = {
|
|
.probe = mixel_mipi_phy_probe,
|
|
.driver = {
|
|
.name = "mixel-mipi-dsi-phy",
|
|
.of_match_table = mixel_mipi_phy_of_match,
|
|
}
|
|
};
|
|
module_platform_driver(mixel_mipi_phy_driver);
|
|
|
|
MODULE_AUTHOR("NXP Semiconductor");
|
|
MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|