259 lines
5.8 KiB
C
259 lines
5.8 KiB
C
/*
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* Copyright 2017-2018 NXP.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define TPM_GLOBAL 0x8
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#define TPM_SC 0x10
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#define TPM_CNT 0x14
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#define TPM_MOD 0x18
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#define TPM_C0SC 0x20
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#define TPM_C0V 0x24
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#define SC_CMOD 3
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#define SC_CPWMS BIT(5)
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#define MSnB BIT(5)
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#define MSnA BIT(4)
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#define ELSnB BIT(3)
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#define ELSnA BIT(2)
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#define PERIOD_PERIOD_MAX 0x10000
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#define PERIOD_DIV_MAX 8
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struct tpm_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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};
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static const unsigned int prediv[8] = {
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1, 2, 4, 8, 16, 32, 64, 128
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};
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#define to_tpm_pwm_chip(_chip) container_of(_chip, struct tpm_pwm_chip, chip)
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static int tpm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct tpm_pwm_chip *tpm = to_tpm_pwm_chip(chip);
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int ret, val, div = 0;
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unsigned int period_cycles, duty_cycles;
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unsigned long rate;
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u64 c;
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rate = clk_get_rate(tpm->clk);
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/* calculate the period_cycles and duty_cycles */
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while (1) {
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c = rate / prediv[div];
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c = c * period_ns;
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do_div(c, 1000000000);
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if (c < PERIOD_PERIOD_MAX)
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break;
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div++;
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if (div >= 8)
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return -EINVAL;
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}
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/* enable the clock before writing the register */
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if (!pwm_is_enabled(pwm)) {
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ret = clk_prepare_enable(tpm->clk);
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if (ret)
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return ret;
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}
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/* set the pre-scale */
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val = readl(tpm->base + TPM_SC);
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val &= ~0x7;
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val |= div;
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writel(val, tpm->base + TPM_SC);
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period_cycles = c;
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c *= duty_ns;
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do_div(c, period_ns);
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duty_cycles = c;
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writel(period_cycles & 0xffff, tpm->base + TPM_MOD);
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writel(duty_cycles & 0xffff, tpm->base + TPM_C0V + pwm->hwpwm * 0x8);
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/* if pwm is not enabled, disable clk after setting */
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if (!pwm_is_enabled(pwm))
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clk_disable_unprepare(tpm->clk);
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return 0;
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}
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static int tpm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tpm_pwm_chip *tpm = to_tpm_pwm_chip(chip);
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int val;
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clk_prepare_enable(tpm->clk);
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/*
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* To enable a tpm channel, CPWMS = 0, MSnB:MSnA = 0x0,
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* for TPM normal polarity ELSnB:ELSnA = 2b'10,
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* inverse ELSnB:ELSnA = 2b'01
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*/
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val = readl(tpm->base + TPM_C0SC + pwm->hwpwm * 0x8);
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val &= ~(MSnB | MSnA | ELSnB | ELSnA);
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val |= MSnB;
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val |= pwm->state.polarity ? ELSnA : ELSnB;
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writel(val, tpm->base + TPM_C0SC + pwm->hwpwm * 0x8);
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/* start the counter */
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val = readl(tpm->base + TPM_SC);
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val |= 0x1 << SC_CMOD;
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writel(val, tpm->base + TPM_SC);
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return 0;
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}
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static void tpm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tpm_pwm_chip *tpm = to_tpm_pwm_chip(chip);
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clk_disable_unprepare(tpm->clk);
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}
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static int tpm_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct tpm_pwm_chip *tpm = to_tpm_pwm_chip(chip);
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int ret, val;
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/* enable the clock before writing the register */
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if (!pwm_is_enabled(pwm)) {
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ret = clk_prepare_enable(tpm->clk);
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if (ret)
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return ret;
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}
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val = readl(tpm->base + TPM_C0SC + pwm->hwpwm * 0x8);
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val &= ~(ELSnB | ELSnA);
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val |= pwm->state.polarity ? ELSnA : ELSnB;
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writel(val, tpm->base + TPM_C0SC + pwm->hwpwm * 0x8);
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if (!pwm_is_enabled(pwm))
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clk_disable_unprepare(tpm->clk);
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return 0;
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}
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static const struct pwm_ops tpm_pwm_ops = {
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.config = tpm_pwm_config,
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.enable = tpm_pwm_enable,
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.disable = tpm_pwm_disable,
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.set_polarity = tpm_pwm_set_polarity,
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.owner = THIS_MODULE,
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};
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static int tpm_pwm_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct tpm_pwm_chip *tpm;
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struct resource *res;
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int ret;
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tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL);
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if (!tpm)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tpm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(tpm->base))
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return PTR_ERR(tpm->base);
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tpm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(tpm->clk))
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return PTR_ERR(tpm->clk);
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tpm->chip.dev = &pdev->dev;
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tpm->chip.ops = &tpm_pwm_ops;
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tpm->chip.base = -1;
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/*
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* init the number of pwm in the pwm chip. if no "fsl,pwm-number"
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* found, init the npwm to 2, as tpm module has at least two pwm channel
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*/
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ret = of_property_read_u32(np, "nxp,pwm-number", &tpm->chip.npwm);
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if (ret < 0) {
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dev_info(&pdev->dev, "default two pwm channel");
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tpm->chip.npwm = 2;
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}
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ret = pwmchip_add(&tpm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, tpm);
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return 0;
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}
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static int tpm_pwm_remove(struct platform_device *pdev)
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{
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struct tpm_pwm_chip *tpm = platform_get_drvdata(pdev);
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return pwmchip_remove(&tpm->chip);
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}
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#ifdef CONFIG_PM_SLEEP
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static int tpm_pwm_suspend(struct device *dev)
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{
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pinctrl_pm_select_sleep_state(dev);
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return 0;
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}
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static int tpm_pwm_resume(struct device *dev)
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{
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pinctrl_pm_select_default_state(dev);
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return 0;
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};
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#endif
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static SIMPLE_DEV_PM_OPS(tpm_pwm_pm, tpm_pwm_suspend, tpm_pwm_resume);
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static const struct of_device_id tpm_pwm_dt_ids[] = {
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{ .compatible = "nxp,tpm-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, tpm_pwm_dt_ids);
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static struct platform_driver tpm_pwm_driver = {
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.driver = {
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.name = "tpm-pwm",
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.of_match_table = tpm_pwm_dt_ids,
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.pm = &tpm_pwm_pm,
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},
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.probe = tpm_pwm_probe,
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.remove = tpm_pwm_remove,
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};
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module_platform_driver(tpm_pwm_driver);
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MODULE_ALIAS("platform:tpm-pwm");
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MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
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MODULE_DESCRIPTION("NXP TPM PWM Driver");
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MODULE_LICENSE("GPL v2");
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