68bab8662f
In certain boards the source for the clk32k clock can be gated. In these boards the clk32k clock can be provided to the driver and it is going to be enabled/disabled when it is needed. If the clk32k clock is not provided the driver will assume that it is always running. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
270 lines
7.1 KiB
C
270 lines
7.1 KiB
C
/*
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* MFD driver for twl6040
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*
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* Authors: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
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* Misael Lopez Cruz <misael.lopez@ti.com>
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*
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* Copyright: (C) 2011 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __TWL6040_CODEC_H__
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#define __TWL6040_CODEC_H__
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/regulator/consumer.h>
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#include <linux/clk.h>
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#define TWL6040_REG_ASICID 0x01
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#define TWL6040_REG_ASICREV 0x02
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#define TWL6040_REG_INTID 0x03
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#define TWL6040_REG_INTMR 0x04
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#define TWL6040_REG_NCPCTL 0x05
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#define TWL6040_REG_LDOCTL 0x06
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#define TWL6040_REG_HPPLLCTL 0x07
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#define TWL6040_REG_LPPLLCTL 0x08
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#define TWL6040_REG_LPPLLDIV 0x09
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#define TWL6040_REG_AMICBCTL 0x0A
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#define TWL6040_REG_DMICBCTL 0x0B
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#define TWL6040_REG_MICLCTL 0x0C
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#define TWL6040_REG_MICRCTL 0x0D
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#define TWL6040_REG_MICGAIN 0x0E
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#define TWL6040_REG_LINEGAIN 0x0F
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#define TWL6040_REG_HSLCTL 0x10
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#define TWL6040_REG_HSRCTL 0x11
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#define TWL6040_REG_HSGAIN 0x12
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#define TWL6040_REG_EARCTL 0x13
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#define TWL6040_REG_HFLCTL 0x14
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#define TWL6040_REG_HFLGAIN 0x15
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#define TWL6040_REG_HFRCTL 0x16
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#define TWL6040_REG_HFRGAIN 0x17
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#define TWL6040_REG_VIBCTLL 0x18
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#define TWL6040_REG_VIBDATL 0x19
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#define TWL6040_REG_VIBCTLR 0x1A
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#define TWL6040_REG_VIBDATR 0x1B
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#define TWL6040_REG_HKCTL1 0x1C
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#define TWL6040_REG_HKCTL2 0x1D
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#define TWL6040_REG_GPOCTL 0x1E
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#define TWL6040_REG_ALB 0x1F
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#define TWL6040_REG_DLB 0x20
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#define TWL6040_REG_TRIM1 0x28
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#define TWL6040_REG_TRIM2 0x29
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#define TWL6040_REG_TRIM3 0x2A
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#define TWL6040_REG_HSOTRIM 0x2B
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#define TWL6040_REG_HFOTRIM 0x2C
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#define TWL6040_REG_ACCCTL 0x2D
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#define TWL6040_REG_STATUS 0x2E
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/* INTID (0x03) fields */
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#define TWL6040_THINT 0x01
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#define TWL6040_PLUGINT 0x02
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#define TWL6040_UNPLUGINT 0x04
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#define TWL6040_HOOKINT 0x08
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#define TWL6040_HFINT 0x10
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#define TWL6040_VIBINT 0x20
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#define TWL6040_READYINT 0x40
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/* INTMR (0x04) fields */
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#define TWL6040_THMSK 0x01
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#define TWL6040_PLUGMSK 0x02
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#define TWL6040_HOOKMSK 0x08
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#define TWL6040_HFMSK 0x10
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#define TWL6040_VIBMSK 0x20
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#define TWL6040_READYMSK 0x40
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#define TWL6040_ALLINT_MSK 0x7B
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/* NCPCTL (0x05) fields */
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#define TWL6040_NCPENA 0x01
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#define TWL6040_NCPOPEN 0x40
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/* LDOCTL (0x06) fields */
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#define TWL6040_LSLDOENA 0x01
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#define TWL6040_HSLDOENA 0x04
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#define TWL6040_REFENA 0x40
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#define TWL6040_OSCENA 0x80
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/* HPPLLCTL (0x07) fields */
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#define TWL6040_HPLLENA 0x01
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#define TWL6040_HPLLRST 0x02
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#define TWL6040_HPLLBP 0x04
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#define TWL6040_HPLLSQRENA 0x08
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#define TWL6040_MCLK_12000KHZ (0 << 5)
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#define TWL6040_MCLK_19200KHZ (1 << 5)
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#define TWL6040_MCLK_26000KHZ (2 << 5)
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#define TWL6040_MCLK_38400KHZ (3 << 5)
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#define TWL6040_MCLK_MSK 0x60
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/* LPPLLCTL (0x08) fields */
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#define TWL6040_LPLLENA 0x01
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#define TWL6040_LPLLRST 0x02
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#define TWL6040_LPLLSEL 0x04
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#define TWL6040_LPLLFIN 0x08
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#define TWL6040_HPLLSEL 0x10
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/* HSLCTL/R (0x10/0x11) fields */
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#define TWL6040_HSDACENA (1 << 0)
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#define TWL6040_HSDACMODE (1 << 1)
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#define TWL6040_HSDRVENA (1 << 2)
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#define TWL6040_HSDRVMODE (1 << 3)
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/* HFLCTL/R (0x14/0x16) fields */
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#define TWL6040_HFDACENA (1 << 0)
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#define TWL6040_HFPGAENA (1 << 1)
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#define TWL6040_HFDRVENA (1 << 4)
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/* VIBCTLL/R (0x18/0x1A) fields */
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#define TWL6040_VIBENA (1 << 0)
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#define TWL6040_VIBSEL (1 << 1)
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#define TWL6040_VIBCTRL (1 << 2)
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#define TWL6040_VIBCTRL_P (1 << 3)
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#define TWL6040_VIBCTRL_N (1 << 4)
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/* VIBDATL/R (0x19/0x1B) fields */
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#define TWL6040_VIBDAT_MAX 0x64
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/* GPOCTL (0x1E) fields */
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#define TWL6040_GPO1 0x01
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#define TWL6040_GPO2 0x02
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#define TWL6040_GPO3 0x04
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/* ACCCTL (0x2D) fields */
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#define TWL6040_I2CSEL 0x01
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#define TWL6040_RESETSPLIT 0x04
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#define TWL6040_INTCLRMODE 0x08
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#define TWL6040_I2CMODE(x) ((x & 0x3) << 4)
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/* STATUS (0x2E) fields */
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#define TWL6040_PLUGCOMP 0x02
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#define TWL6040_VIBLOCDET 0x10
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#define TWL6040_VIBROCDET 0x20
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#define TWL6040_TSHUTDET 0x40
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#define TWL6040_CELLS 3
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#define TWL6040_REV_ES1_0 0x00
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#define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */
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#define TWL6040_REV_ES1_3 0x02
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#define TWL6041_REV_ES2_0 0x10
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#define TWL6040_IRQ_TH 0
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#define TWL6040_IRQ_PLUG 1
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#define TWL6040_IRQ_HOOK 2
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#define TWL6040_IRQ_HF 3
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#define TWL6040_IRQ_VIB 4
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#define TWL6040_IRQ_READY 5
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/* PLL selection */
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#define TWL6040_SYSCLK_SEL_LPPLL 0
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#define TWL6040_SYSCLK_SEL_HPPLL 1
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#define TWL6040_GPO_MAX 3
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/* TODO: All platform data struct can be removed */
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struct twl6040_codec_data {
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u16 hs_left_step;
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u16 hs_right_step;
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u16 hf_left_step;
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u16 hf_right_step;
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};
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struct twl6040_vibra_data {
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unsigned int vibldrv_res; /* left driver resistance */
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unsigned int vibrdrv_res; /* right driver resistance */
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unsigned int viblmotor_res; /* left motor resistance */
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unsigned int vibrmotor_res; /* right motor resistance */
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int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */
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int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */
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};
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struct twl6040_gpo_data {
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int gpio_base;
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};
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struct twl6040_platform_data {
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int audpwron_gpio; /* audio power-on gpio */
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struct twl6040_codec_data *codec;
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struct twl6040_vibra_data *vibra;
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struct twl6040_gpo_data *gpo;
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};
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struct regmap;
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struct regmap_irq_chips_data;
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struct twl6040 {
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_data;
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struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
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struct clk *clk32k;
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struct mutex mutex;
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struct mutex irq_mutex;
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struct mfd_cell cells[TWL6040_CELLS];
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struct completion ready;
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int audpwron;
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int power_count;
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int rev;
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/* PLL configuration */
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int pll;
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unsigned int sysclk;
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unsigned int mclk;
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unsigned int irq;
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unsigned int irq_ready;
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unsigned int irq_th;
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};
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int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
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int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
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u8 val);
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int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
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u8 mask);
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int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
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u8 mask);
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int twl6040_power(struct twl6040 *twl6040, int on);
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int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
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unsigned int freq_in, unsigned int freq_out);
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int twl6040_get_pll(struct twl6040 *twl6040);
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unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
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/* Get the combined status of the vibra control register */
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int twl6040_get_vibralr_status(struct twl6040 *twl6040);
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static inline int twl6040_get_revid(struct twl6040 *twl6040)
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{
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return twl6040->rev;
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}
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#endif /* End of __TWL6040_CODEC_H__ */
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