0bc09f9cdc
Prior to DRA74x silicon rev 1.1, pcie_pcs register bits 8-15 and bits 16-23 were used to configure RC delay count for phy1 and phy2 respectively. phyid was used as index to distinguish the phys and to configure the delay values appropriately. As of DRA74x silicon rev 1.1, pcie_pcs register definition has changed. Bits 16-23 are used to configure delay values for *both* phy1 and phy2. Hence phyid is no longer required. So, drop id field from ti_pipe3 structure and its subsequent references for configuring pcie_pcs register. Also, pcie_pcs register now needs to be configured with delay value of 0x96 at bit positions 16-23. See register description of CTRL_CORE_PCIE_PCS in ARM572x TRM, SPRUHZ6, October 2014, section 18.5.2.2, table 18-1804. This is needed to ensure Gen2 cards are enumerated consistently. DRA72x silicon behaves same way as DRA74x rev 1.1 as far as this functionality is considered. Test results on DRA74x and DRA72x EVMs: Before patch ------------ DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to silicon errata) DRA74x ES 1.1: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect programming of register DRA72x: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect programming of register After patch ----------- DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to silicon errata) DRA74x ES 1.1: Gen1 cards work, Gen2 cards work consistently. DRA72x: Gen1 and Gen2 cards enumerate consistently. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/*
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* omap_control_phy.h - Header file for the PHY part of control module.
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __OMAP_CONTROL_PHY_H__
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#define __OMAP_CONTROL_PHY_H__
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enum omap_control_phy_type {
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OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */
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OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */
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OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
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OMAP_CTRL_TYPE_PCIE, /* RX TX control of ACSPCIE */
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OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
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OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
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};
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struct omap_control_phy {
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struct device *dev;
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u32 __iomem *otghs_control;
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u32 __iomem *power;
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u32 __iomem *power_aux;
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u32 __iomem *pcie_pcs;
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struct clk *sys_clk;
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enum omap_control_phy_type type;
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};
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enum omap_control_usb_mode {
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USB_MODE_UNDEFINED = 0,
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USB_MODE_HOST,
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USB_MODE_DEVICE,
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USB_MODE_DISCONNECT,
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};
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#define OMAP_CTRL_DEV_PHY_PD BIT(0)
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#define OMAP_CTRL_DEV_AVALID BIT(0)
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#define OMAP_CTRL_DEV_BVALID BIT(1)
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#define OMAP_CTRL_DEV_VBUSVALID BIT(2)
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#define OMAP_CTRL_DEV_SESSEND BIT(3)
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#define OMAP_CTRL_DEV_IDDIG BIT(4)
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
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#define OMAP_CTRL_PCIE_PCS_MASK 0xff
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#define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 16
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#define OMAP_CTRL_USB2_PHY_PD BIT(28)
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#define AM437X_CTRL_USB2_PHY_PD BIT(0)
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#define AM437X_CTRL_USB2_OTG_PD BIT(1)
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#define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
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#define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
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#if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
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void omap_control_phy_power(struct device *dev, int on);
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void omap_control_usb_set_mode(struct device *dev,
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enum omap_control_usb_mode mode);
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void omap_control_pcie_pcs(struct device *dev, u8 delay);
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#else
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static inline void omap_control_phy_power(struct device *dev, int on)
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{
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}
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static inline void omap_control_usb_set_mode(struct device *dev,
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enum omap_control_usb_mode mode)
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{
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}
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static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
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{
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}
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#endif
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#endif /* __OMAP_CONTROL_PHY_H__ */
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