fef775caa7
This commit adds a new platform-data boolean property that enables use of a flash-based bad block table. This can also be enabled by setting the 'nand-on-flash-bbt' devicetree property. If the flash BBT is not enabled, the driver falls back to use OOB bad block markers only, as before. If the flash BBT is enabled the kernel will keep track of bad blocks using a BBT, in addition to the OOB markers. As explained by Brian Norris the reasons for using a BBT are: "" The primary reason would be that NAND datasheets specify it these days. A better argument is that nobody guarantees that you can write a bad block marker to a worn out block; you may just get program failures. This has been acknowledged by several developers over the last several years. Additionally, you get a boot-time performance improvement if you only have to read a few pages, instead of a page or two from every block on the flash. "" Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/*
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* Copyright (C) 2006 Micron Technology Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _MTD_NAND_OMAP2_H
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#define _MTD_NAND_OMAP2_H
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#include <linux/mtd/partitions.h>
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#define GPMC_BCH_NUM_REMAINDER 8
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enum nand_io {
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NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
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NAND_OMAP_POLLED, /* polled mode, without prefetch */
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NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
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NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
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};
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enum omap_ecc {
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/*
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* 1-bit ECC: calculation and correction by SW
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* ECC stored at end of spare area
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*/
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OMAP_ECC_HAM1_CODE_SW = 0,
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/*
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* 1-bit ECC: calculation by GPMC, Error detection by Software
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* ECC layout compatible with ROM code layout
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*/
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OMAP_ECC_HAM1_CODE_HW,
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/* 4-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
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/* 4-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH4_CODE_HW,
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/* 8-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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/* 8-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH8_CODE_HW,
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/* 16-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH16_CODE_HW,
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};
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struct gpmc_nand_regs {
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void __iomem *gpmc_status;
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void __iomem *gpmc_nand_command;
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void __iomem *gpmc_nand_address;
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void __iomem *gpmc_nand_data;
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void __iomem *gpmc_prefetch_config1;
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void __iomem *gpmc_prefetch_config2;
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void __iomem *gpmc_prefetch_control;
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void __iomem *gpmc_prefetch_status;
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void __iomem *gpmc_ecc_config;
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void __iomem *gpmc_ecc_control;
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void __iomem *gpmc_ecc_size_config;
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void __iomem *gpmc_ecc1_result;
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void __iomem *gpmc_bch_result0[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
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void __iomem *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
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};
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struct omap_nand_platform_data {
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int cs;
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struct mtd_partition *parts;
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int nr_parts;
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bool dev_ready;
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bool flash_bbt;
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enum nand_io xfer_type;
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int devsize;
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enum omap_ecc ecc_opt;
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struct gpmc_nand_regs reg;
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/* for passing the partitions */
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struct device_node *of_node;
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struct device_node *elm_of_node;
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};
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#endif
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