c4f6c41ba7
Add support for HPB-DMAC found in Renesas R-Car SoCs, using 'shdma-base' DMA driver framework. Based on the original patch by Phil Edworthy <phil.edworthy@renesas.com>. Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: removed useless #include, sorted #include's, fixed HPB_DMA_TCR_MAX, fixed formats and removed line breaks in the dev_dbg() calls, rephrased and added IRQ # to the shdma_request_irq() failure message, added MODULE_AUTHOR(), removed '__init'/'__exit' annotations from the probe()/remove() methods, removed '__initdata' annotation from 'hpb_dmae_driver', fixed guard macro name in the header file, fixed #define ASYNCRSTR_ASRST20, added #define ASYNCRSTR_ASRST24, added the necessary runtime PM calls to the probe() and remove() methods, handled errors returned by dma_async_device_register(), beautified comments and #define's.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
/*
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* Copyright (C) 2011-2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*/
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#ifndef __DMA_RCAR_HPBDMA_H
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#define __DMA_RCAR_HPBDMA_H
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#include <linux/bitops.h>
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#include <linux/types.h>
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/* Transmit sizes and respective register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_MAX
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};
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/* DMA control register (DCR) bits */
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#define HPB_DMAE_DCR_DTAMD (1u << 26)
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#define HPB_DMAE_DCR_DTAC (1u << 25)
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#define HPB_DMAE_DCR_DTAU (1u << 24)
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#define HPB_DMAE_DCR_DTAU1 (1u << 23)
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#define HPB_DMAE_DCR_SWMD (1u << 22)
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#define HPB_DMAE_DCR_BTMD (1u << 21)
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#define HPB_DMAE_DCR_PKMD (1u << 20)
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#define HPB_DMAE_DCR_CT (1u << 18)
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#define HPB_DMAE_DCR_ACMD (1u << 17)
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#define HPB_DMAE_DCR_DIP (1u << 16)
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#define HPB_DMAE_DCR_SMDL (1u << 13)
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#define HPB_DMAE_DCR_SPDAM (1u << 12)
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#define HPB_DMAE_DCR_SDRMD_MASK (3u << 10)
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#define HPB_DMAE_DCR_SDRMD_MOD (0u << 10)
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#define HPB_DMAE_DCR_SDRMD_AUTO (1u << 10)
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#define HPB_DMAE_DCR_SDRMD_TIMER (2u << 10)
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#define HPB_DMAE_DCR_SPDS_MASK (3u << 8)
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#define HPB_DMAE_DCR_SPDS_8BIT (0u << 8)
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#define HPB_DMAE_DCR_SPDS_16BIT (1u << 8)
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#define HPB_DMAE_DCR_SPDS_32BIT (2u << 8)
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#define HPB_DMAE_DCR_DMDL (1u << 5)
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#define HPB_DMAE_DCR_DPDAM (1u << 4)
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#define HPB_DMAE_DCR_DDRMD_MASK (3u << 2)
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#define HPB_DMAE_DCR_DDRMD_MOD (0u << 2)
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#define HPB_DMAE_DCR_DDRMD_AUTO (1u << 2)
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#define HPB_DMAE_DCR_DDRMD_TIMER (2u << 2)
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#define HPB_DMAE_DCR_DPDS_MASK (3u << 0)
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#define HPB_DMAE_DCR_DPDS_8BIT (0u << 0)
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#define HPB_DMAE_DCR_DPDS_16BIT (1u << 0)
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#define HPB_DMAE_DCR_DPDS_32BIT (2u << 0)
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/* Asynchronous reset register (ASYNCRSTR) bits */
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#define HPB_DMAE_ASYNCRSTR_ASRST41 BIT(10)
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#define HPB_DMAE_ASYNCRSTR_ASRST40 BIT(9)
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#define HPB_DMAE_ASYNCRSTR_ASRST39 BIT(8)
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#define HPB_DMAE_ASYNCRSTR_ASRST27 BIT(7)
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#define HPB_DMAE_ASYNCRSTR_ASRST26 BIT(6)
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#define HPB_DMAE_ASYNCRSTR_ASRST25 BIT(5)
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#define HPB_DMAE_ASYNCRSTR_ASRST24 BIT(4)
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#define HPB_DMAE_ASYNCRSTR_ASRST23 BIT(3)
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#define HPB_DMAE_ASYNCRSTR_ASRST22 BIT(2)
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#define HPB_DMAE_ASYNCRSTR_ASRST21 BIT(1)
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#define HPB_DMAE_ASYNCRSTR_ASRST20 BIT(0)
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struct hpb_dmae_slave_config {
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unsigned int id;
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dma_addr_t addr;
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u32 dcr;
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u32 port;
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u32 rstr;
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u32 mdr;
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u32 mdm;
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u32 flags;
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#define HPB_DMAE_SET_ASYNC_RESET BIT(0)
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#define HPB_DMAE_SET_ASYNC_MODE BIT(1)
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u32 dma_ch;
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};
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#define HPB_DMAE_CHANNEL(_irq, _s_id) \
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{ \
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.ch_irq = _irq, \
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.s_id = _s_id, \
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}
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struct hpb_dmae_channel {
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unsigned int ch_irq;
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unsigned int s_id;
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};
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struct hpb_dmae_pdata {
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const struct hpb_dmae_slave_config *slaves;
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int num_slaves;
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const struct hpb_dmae_channel *channels;
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int num_channels;
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const unsigned int ts_shift[XMIT_SZ_MAX];
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int num_hw_channels;
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};
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#endif
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