5b3e507820
This commit adds support for the user to specify the ECC strength and step size through the devicetree. We keep the previous behavior, when there is no DT parameter provided. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
#ifndef __ASM_ARCH_PXA3XX_NAND_H
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#define __ASM_ARCH_PXA3XX_NAND_H
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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struct pxa3xx_nand_timing {
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unsigned int tCH; /* Enable signal hold time */
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unsigned int tCS; /* Enable signal setup time */
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unsigned int tWH; /* ND_nWE high duration */
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unsigned int tWP; /* ND_nWE pulse time */
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unsigned int tRH; /* ND_nRE high duration */
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unsigned int tRP; /* ND_nRE pulse width */
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unsigned int tR; /* ND_nWE high to ND_nRE low for read */
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unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
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unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
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};
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struct pxa3xx_nand_flash {
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char *name;
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uint32_t chip_id;
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unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
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unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
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unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
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unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
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unsigned int num_blocks; /* Number of physical blocks in Flash */
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struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
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};
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/*
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* Current pxa3xx_nand controller has two chip select which
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* both be workable.
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*
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* Notice should be taken that:
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* When you want to use this feature, you should not enable the
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* keep configuration feature, for two chip select could be
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* attached with different nand chip. The different page size
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* and timing requirement make the keep configuration impossible.
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*/
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/* The max num of chip select current support */
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#define NUM_CHIP_SELECT (2)
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struct pxa3xx_nand_platform_data {
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/* the data flash bus is shared between the Static Memory
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* Controller and the Data Flash Controller, the arbiter
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* controls the ownership of the bus
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*/
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int enable_arbiter;
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/* allow platform code to keep OBM/bootloader defined NFC config */
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int keep_config;
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/* indicate how many chip selects will be used */
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int num_cs;
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/* use an flash-based bad block table */
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bool flash_bbt;
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/* requested ECC strength and ECC step size */
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int ecc_strength, ecc_step_size;
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const struct mtd_partition *parts[NUM_CHIP_SELECT];
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unsigned int nr_parts[NUM_CHIP_SELECT];
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const struct pxa3xx_nand_flash * flash;
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size_t num_flash;
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};
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extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
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#endif /* __ASM_ARCH_PXA3XX_NAND_H */
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