![Zhao Qiang](/assets/img/avatar_default.png)
ls1 has qe and ls1 has arm cpu. move qe from arch/powerpc to drivers/soc/fsl to adapt to powerpc and arm Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* Internal header file for UCC unit routines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __UCC_H__
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#define __UCC_H__
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#define STATISTICS
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#define UCC_MAX_NUM 8
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/* Slow or fast type for UCCs.
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*/
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enum ucc_speed_type {
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UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
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UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
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};
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/* ucc_set_type
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* Sets UCC to slow or fast mode.
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*
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* ucc_num - (In) number of UCC (0-7).
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* speed - (In) slow or fast mode for UCC.
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*/
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int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
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int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
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int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
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enum comm_dir mode);
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int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
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/* QE MUX clock routing for UCC
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*/
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static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
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{
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return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
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}
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static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
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{
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return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
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}
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static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
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{
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return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
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}
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#endif /* __UCC_H__ */
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