![Felipe Balbi](/assets/img/avatar_default.png)
earlier commits have broken compilation of tusb6010 glue layer, fix it. Signed-off-by: Felipe Balbi <balbi@ti.com>
728 lines
19 KiB
C
728 lines
19 KiB
C
/*
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* TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/usb.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <plat/dma.h>
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#include <plat/mux.h>
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#include "musb_core.h"
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#include "tusb6010.h"
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#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
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#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
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struct tusb_omap_dma_ch {
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struct musb *musb;
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void __iomem *tbase;
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unsigned long phys_offset;
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int epnum;
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u8 tx;
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struct musb_hw_ep *hw_ep;
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int ch;
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s8 dmareq;
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s8 sync_dev;
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struct tusb_omap_dma *tusb_dma;
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dma_addr_t dma_addr;
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u32 len;
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u16 packet_sz;
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u16 transfer_packet_sz;
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u32 transfer_len;
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u32 completed_len;
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};
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struct tusb_omap_dma {
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struct dma_controller controller;
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struct musb *musb;
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void __iomem *tbase;
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int ch;
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s8 dmareq;
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s8 sync_dev;
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unsigned multichannel:1;
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};
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static int tusb_omap_dma_start(struct dma_controller *c)
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{
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struct tusb_omap_dma *tusb_dma;
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tusb_dma = container_of(c, struct tusb_omap_dma, controller);
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/* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
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return 0;
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}
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static int tusb_omap_dma_stop(struct dma_controller *c)
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{
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struct tusb_omap_dma *tusb_dma;
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tusb_dma = container_of(c, struct tusb_omap_dma, controller);
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/* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
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return 0;
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}
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/*
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* Allocate dmareq0 to the current channel unless it's already taken
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*/
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static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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if (reg != 0) {
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dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
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chdat->epnum, reg & 0xf);
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return -EAGAIN;
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}
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if (chdat->tx)
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reg = (1 << 4) | chdat->epnum;
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else
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reg = chdat->epnum;
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musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
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return 0;
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}
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static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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if ((reg & 0xf) != chdat->epnum) {
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printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
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chdat->epnum, reg & 0xf);
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return;
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}
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musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
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}
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/*
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* See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
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* musb_gadget.c.
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*/
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static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
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{
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struct dma_channel *channel = (struct dma_channel *)data;
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
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struct musb *musb = chdat->musb;
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struct device *dev = musb->controller;
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struct musb_hw_ep *hw_ep = chdat->hw_ep;
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void __iomem *ep_conf = hw_ep->conf;
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void __iomem *mbase = musb->mregs;
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unsigned long remaining, flags, pio;
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int ch;
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spin_lock_irqsave(&musb->lock, flags);
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if (tusb_dma->multichannel)
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ch = chdat->ch;
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else
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ch = tusb_dma->ch;
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if (ch_status != OMAP_DMA_BLOCK_IRQ)
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printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
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dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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ch, ch_status);
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if (chdat->tx)
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remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
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else
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remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
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remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
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/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
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if (unlikely(remaining > chdat->transfer_len)) {
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dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
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chdat->tx ? "tx" : "rx", chdat->ch,
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remaining);
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remaining = 0;
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}
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channel->actual_len = chdat->transfer_len - remaining;
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pio = chdat->len - channel->actual_len;
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dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
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/* Transfer remaining 1 - 31 bytes */
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if (pio > 0 && pio < 32) {
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u8 *buf;
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dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
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buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
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if (chdat->tx) {
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dma_unmap_single(dev, chdat->dma_addr,
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chdat->transfer_len,
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DMA_TO_DEVICE);
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musb_write_fifo(hw_ep, pio, buf);
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} else {
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dma_unmap_single(dev, chdat->dma_addr,
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chdat->transfer_len,
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DMA_FROM_DEVICE);
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musb_read_fifo(hw_ep, pio, buf);
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}
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channel->actual_len += pio;
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}
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if (!tusb_dma->multichannel)
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tusb_omap_free_shared_dmareq(chdat);
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channel->status = MUSB_DMA_STATUS_FREE;
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/* Handle only RX callbacks here. TX callbacks must be handled based
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* on the TUSB DMA status interrupt.
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* REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
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* interrupt for RX and TX.
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*/
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if (!chdat->tx)
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musb_dma_completion(musb, chdat->epnum, chdat->tx);
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/* We must terminate short tx transfers manually by setting TXPKTRDY.
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* REVISIT: This same problem may occur with other MUSB dma as well.
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* Easy to test with g_ether by pinging the MUSB board with ping -s54.
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*/
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if ((chdat->transfer_len < chdat->packet_sz)
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|| (chdat->transfer_len % chdat->packet_sz != 0)) {
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u16 csr;
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if (chdat->tx) {
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dev_dbg(musb->controller, "terminating short tx packet\n");
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musb_ep_select(mbase, chdat->epnum);
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csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
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csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
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| MUSB_TXCSR_P_WZC_BITS;
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musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
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}
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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u8 rndis_mode, dma_addr_t dma_addr, u32 len)
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{
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
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struct musb *musb = chdat->musb;
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struct device *dev = musb->controller;
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struct musb_hw_ep *hw_ep = chdat->hw_ep;
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void __iomem *mbase = musb->mregs;
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void __iomem *ep_conf = hw_ep->conf;
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dma_addr_t fifo = hw_ep->fifo_sync;
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struct omap_dma_channel_params dma_params;
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u32 dma_remaining;
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int src_burst, dst_burst;
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u16 csr;
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int ch;
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s8 dmareq;
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s8 sync_dev;
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if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
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return false;
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/*
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* HW issue #10: Async dma will eventually corrupt the XFR_SIZE
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* register which will cause missed DMA interrupt. We could try to
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* use a timer for the callback, but it is unsafe as the XFR_SIZE
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* register is corrupt, and we won't know if the DMA worked.
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*/
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if (dma_addr & 0x2)
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return false;
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/*
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* Because of HW issue #10, it seems like mixing sync DMA and async
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* PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
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* using the channel for DMA.
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*/
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if (chdat->tx)
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dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
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else
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dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
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dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
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if (dma_remaining) {
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dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
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chdat->tx ? "tx" : "rx", chdat->ch,
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dma_remaining);
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return false;
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}
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chdat->transfer_len = len & ~0x1f;
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if (len < packet_sz)
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chdat->transfer_packet_sz = chdat->transfer_len;
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else
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chdat->transfer_packet_sz = packet_sz;
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if (tusb_dma->multichannel) {
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ch = chdat->ch;
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dmareq = chdat->dmareq;
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sync_dev = chdat->sync_dev;
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} else {
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if (tusb_omap_use_shared_dmareq(chdat) != 0) {
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dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
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return false;
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}
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if (tusb_dma->ch < 0) {
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/* REVISIT: This should get blocked earlier, happens
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* with MSC ErrorRecoveryTest
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*/
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WARN_ON(1);
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return false;
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}
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ch = tusb_dma->ch;
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dmareq = tusb_dma->dmareq;
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sync_dev = tusb_dma->sync_dev;
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omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
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}
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chdat->packet_sz = packet_sz;
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chdat->len = len;
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channel->actual_len = 0;
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chdat->dma_addr = dma_addr;
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channel->status = MUSB_DMA_STATUS_BUSY;
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/* Since we're recycling dma areas, we need to clean or invalidate */
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if (chdat->tx)
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dma_map_single(dev, phys_to_virt(dma_addr), len,
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DMA_TO_DEVICE);
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else
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dma_map_single(dev, phys_to_virt(dma_addr), len,
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DMA_FROM_DEVICE);
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/* Use 16-bit transfer if dma_addr is not 32-bit aligned */
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if ((dma_addr & 0x3) == 0) {
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dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
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dma_params.elem_count = 8; /* Elements in frame */
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} else {
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dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
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dma_params.elem_count = 16; /* Elements in frame */
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fifo = hw_ep->fifo_async;
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}
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dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
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dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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ch, dma_addr, chdat->transfer_len, len,
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chdat->transfer_packet_sz, packet_sz);
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/*
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* Prepare omap DMA for transfer
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*/
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if (chdat->tx) {
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dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
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dma_params.src_start = (unsigned long)dma_addr;
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dma_params.src_ei = 0;
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dma_params.src_fi = 0;
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dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
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dma_params.dst_start = (unsigned long)fifo;
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dma_params.dst_ei = 1;
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dma_params.dst_fi = -31; /* Loop 32 byte window */
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dma_params.trigger = sync_dev;
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dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
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dma_params.src_or_dst_synch = 0; /* Dest sync */
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src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
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dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
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} else {
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dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
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dma_params.src_start = (unsigned long)fifo;
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dma_params.src_ei = 1;
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dma_params.src_fi = -31; /* Loop 32 byte window */
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dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
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dma_params.dst_start = (unsigned long)dma_addr;
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dma_params.dst_ei = 0;
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dma_params.dst_fi = 0;
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dma_params.trigger = sync_dev;
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dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
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dma_params.src_or_dst_synch = 1; /* Source sync */
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src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
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dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
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}
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dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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(dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
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((dma_addr & 0x3) == 0) ? "sync" : "async",
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dma_params.src_start, dma_params.dst_start);
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omap_set_dma_params(ch, &dma_params);
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omap_set_dma_src_burst_mode(ch, src_burst);
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omap_set_dma_dest_burst_mode(ch, dst_burst);
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omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
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/*
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* Prepare MUSB for DMA transfer
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*/
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if (chdat->tx) {
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musb_ep_select(mbase, chdat->epnum);
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csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
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csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
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| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
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csr &= ~MUSB_TXCSR_P_UNDERRUN;
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musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
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} else {
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musb_ep_select(mbase, chdat->epnum);
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csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
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csr |= MUSB_RXCSR_DMAENAB;
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csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
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musb_writew(hw_ep->regs, MUSB_RXCSR,
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csr | MUSB_RXCSR_P_WZC_BITS);
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}
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/*
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* Start DMA transfer
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*/
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omap_start_dma(ch);
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if (chdat->tx) {
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/* Send transfer_packet_sz packets at a time */
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musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
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chdat->transfer_packet_sz);
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musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
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TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
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} else {
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/* Receive transfer_packet_sz packets at a time */
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musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
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chdat->transfer_packet_sz << 16);
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musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
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TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
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}
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return true;
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}
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static int tusb_omap_dma_abort(struct dma_channel *channel)
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{
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
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if (!tusb_dma->multichannel) {
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if (tusb_dma->ch >= 0) {
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omap_stop_dma(tusb_dma->ch);
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omap_free_dma(tusb_dma->ch);
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tusb_dma->ch = -1;
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}
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tusb_dma->dmareq = -1;
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tusb_dma->sync_dev = -1;
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}
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channel->status = MUSB_DMA_STATUS_FREE;
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return 0;
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}
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static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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int i, dmareq_nr = -1;
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const int sync_dev[6] = {
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OMAP24XX_DMA_EXT_DMAREQ0,
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OMAP24XX_DMA_EXT_DMAREQ1,
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OMAP242X_DMA_EXT_DMAREQ2,
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OMAP242X_DMA_EXT_DMAREQ3,
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OMAP242X_DMA_EXT_DMAREQ4,
|
|
OMAP242X_DMA_EXT_DMAREQ5,
|
|
};
|
|
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
int cur = (reg & (0xf << (i * 5))) >> (i * 5);
|
|
if (cur == 0) {
|
|
dmareq_nr = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (dmareq_nr == -1)
|
|
return -EAGAIN;
|
|
|
|
reg |= (chdat->epnum << (dmareq_nr * 5));
|
|
if (chdat->tx)
|
|
reg |= ((1 << 4) << (dmareq_nr * 5));
|
|
musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
|
|
|
|
chdat->dmareq = dmareq_nr;
|
|
chdat->sync_dev = sync_dev[chdat->dmareq];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
|
|
{
|
|
u32 reg;
|
|
|
|
if (!chdat || chdat->dmareq < 0)
|
|
return;
|
|
|
|
reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
|
|
reg &= ~(0x1f << (chdat->dmareq * 5));
|
|
musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
|
|
|
|
chdat->dmareq = -1;
|
|
chdat->sync_dev = -1;
|
|
}
|
|
|
|
static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
|
|
|
|
static struct dma_channel *
|
|
tusb_omap_dma_allocate(struct dma_controller *c,
|
|
struct musb_hw_ep *hw_ep,
|
|
u8 tx)
|
|
{
|
|
int ret, i;
|
|
const char *dev_name;
|
|
struct tusb_omap_dma *tusb_dma;
|
|
struct musb *musb;
|
|
void __iomem *tbase;
|
|
struct dma_channel *channel = NULL;
|
|
struct tusb_omap_dma_ch *chdat = NULL;
|
|
u32 reg;
|
|
|
|
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
|
|
musb = tusb_dma->musb;
|
|
tbase = musb->ctrl_base;
|
|
|
|
reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
|
|
if (tx)
|
|
reg &= ~(1 << hw_ep->epnum);
|
|
else
|
|
reg &= ~(1 << (hw_ep->epnum + 15));
|
|
musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
|
|
|
|
/* REVISIT: Why does dmareq5 not work? */
|
|
if (hw_ep->epnum == 0) {
|
|
dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
|
|
return NULL;
|
|
}
|
|
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
struct dma_channel *ch = dma_channel_pool[i];
|
|
if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
|
|
ch->status = MUSB_DMA_STATUS_FREE;
|
|
channel = ch;
|
|
chdat = ch->private_data;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!channel)
|
|
return NULL;
|
|
|
|
if (tx) {
|
|
chdat->tx = 1;
|
|
dev_name = "TUSB transmit";
|
|
} else {
|
|
chdat->tx = 0;
|
|
dev_name = "TUSB receive";
|
|
}
|
|
|
|
chdat->musb = tusb_dma->musb;
|
|
chdat->tbase = tusb_dma->tbase;
|
|
chdat->hw_ep = hw_ep;
|
|
chdat->epnum = hw_ep->epnum;
|
|
chdat->dmareq = -1;
|
|
chdat->completed_len = 0;
|
|
chdat->tusb_dma = tusb_dma;
|
|
|
|
channel->max_len = 0x7fffffff;
|
|
channel->desired_mode = 0;
|
|
channel->actual_len = 0;
|
|
|
|
if (tusb_dma->multichannel) {
|
|
ret = tusb_omap_dma_allocate_dmareq(chdat);
|
|
if (ret != 0)
|
|
goto free_dmareq;
|
|
|
|
ret = omap_request_dma(chdat->sync_dev, dev_name,
|
|
tusb_omap_dma_cb, channel, &chdat->ch);
|
|
if (ret != 0)
|
|
goto free_dmareq;
|
|
} else if (tusb_dma->ch == -1) {
|
|
tusb_dma->dmareq = 0;
|
|
tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
|
|
|
|
/* Callback data gets set later in the shared dmareq case */
|
|
ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
|
|
tusb_omap_dma_cb, NULL, &tusb_dma->ch);
|
|
if (ret != 0)
|
|
goto free_dmareq;
|
|
|
|
chdat->dmareq = -1;
|
|
chdat->ch = -1;
|
|
}
|
|
|
|
dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
|
|
chdat->epnum,
|
|
chdat->tx ? "tx" : "rx",
|
|
chdat->ch >= 0 ? "dedicated" : "shared",
|
|
chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
|
|
chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
|
|
chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
|
|
|
|
return channel;
|
|
|
|
free_dmareq:
|
|
tusb_omap_dma_free_dmareq(chdat);
|
|
|
|
dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
|
|
channel->status = MUSB_DMA_STATUS_UNKNOWN;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void tusb_omap_dma_release(struct dma_channel *channel)
|
|
{
|
|
struct tusb_omap_dma_ch *chdat = to_chdat(channel);
|
|
struct musb *musb = chdat->musb;
|
|
void __iomem *tbase = musb->ctrl_base;
|
|
u32 reg;
|
|
|
|
dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
|
|
|
|
reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
|
|
if (chdat->tx)
|
|
reg |= (1 << chdat->epnum);
|
|
else
|
|
reg |= (1 << (chdat->epnum + 15));
|
|
musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
|
|
|
|
reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
|
|
if (chdat->tx)
|
|
reg |= (1 << chdat->epnum);
|
|
else
|
|
reg |= (1 << (chdat->epnum + 15));
|
|
musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
|
|
|
|
channel->status = MUSB_DMA_STATUS_UNKNOWN;
|
|
|
|
if (chdat->ch >= 0) {
|
|
omap_stop_dma(chdat->ch);
|
|
omap_free_dma(chdat->ch);
|
|
chdat->ch = -1;
|
|
}
|
|
|
|
if (chdat->dmareq >= 0)
|
|
tusb_omap_dma_free_dmareq(chdat);
|
|
|
|
channel = NULL;
|
|
}
|
|
|
|
void dma_controller_destroy(struct dma_controller *c)
|
|
{
|
|
struct tusb_omap_dma *tusb_dma;
|
|
int i;
|
|
|
|
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
struct dma_channel *ch = dma_channel_pool[i];
|
|
if (ch) {
|
|
kfree(ch->private_data);
|
|
kfree(ch);
|
|
}
|
|
}
|
|
|
|
if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0)
|
|
omap_free_dma(tusb_dma->ch);
|
|
|
|
kfree(tusb_dma);
|
|
}
|
|
|
|
struct dma_controller *__init
|
|
dma_controller_create(struct musb *musb, void __iomem *base)
|
|
{
|
|
void __iomem *tbase = musb->ctrl_base;
|
|
struct tusb_omap_dma *tusb_dma;
|
|
int i;
|
|
|
|
/* REVISIT: Get dmareq lines used from board-*.c */
|
|
|
|
musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
|
|
musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
|
|
|
|
musb_writel(tbase, TUSB_DMA_REQ_CONF,
|
|
TUSB_DMA_REQ_CONF_BURST_SIZE(2)
|
|
| TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
|
|
| TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
|
|
|
|
tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
|
|
if (!tusb_dma)
|
|
goto out;
|
|
|
|
tusb_dma->musb = musb;
|
|
tusb_dma->tbase = musb->ctrl_base;
|
|
|
|
tusb_dma->ch = -1;
|
|
tusb_dma->dmareq = -1;
|
|
tusb_dma->sync_dev = -1;
|
|
|
|
tusb_dma->controller.start = tusb_omap_dma_start;
|
|
tusb_dma->controller.stop = tusb_omap_dma_stop;
|
|
tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
|
|
tusb_dma->controller.channel_release = tusb_omap_dma_release;
|
|
tusb_dma->controller.channel_program = tusb_omap_dma_program;
|
|
tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
|
|
|
|
if (tusb_get_revision(musb) >= TUSB_REV_30)
|
|
tusb_dma->multichannel = 1;
|
|
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
struct dma_channel *ch;
|
|
struct tusb_omap_dma_ch *chdat;
|
|
|
|
ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
|
|
if (!ch)
|
|
goto cleanup;
|
|
|
|
dma_channel_pool[i] = ch;
|
|
|
|
chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
|
|
if (!chdat)
|
|
goto cleanup;
|
|
|
|
ch->status = MUSB_DMA_STATUS_UNKNOWN;
|
|
ch->private_data = chdat;
|
|
}
|
|
|
|
return &tusb_dma->controller;
|
|
|
|
cleanup:
|
|
dma_controller_destroy(&tusb_dma->controller);
|
|
out:
|
|
return NULL;
|
|
}
|