![Mark Rutland](/assets/img/avatar_default.png)
While we currently expect self-hosted debug support to be identical across CPUs, we don't currently sanity check this. This patch adds logging of the ID_AA64DFR{0,1}_EL1 values and associated sanity checking code. It's not clear to me whether we need to check PMUVer, TraceVer, and DebugVer, as we don't currently rely on these fields at all. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
236 lines
7.3 KiB
C
236 lines
7.3 KiB
C
/*
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* Record and handle CPU attributes.
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*
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* Copyright (C) 2014 ARM Ltd.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/arch_timer.h>
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#include <asm/cachetype.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/preempt.h>
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#include <linux/printk.h>
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#include <linux/smp.h>
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/*
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* In case the boot CPU is hotpluggable, we record its initial state and
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* current state separately. Certain system registers may contain different
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* values depending on configuration at or after reset.
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*/
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DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
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static struct cpuinfo_arm64 boot_cpu_data;
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static char *icache_policy_str[] = {
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[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
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[ICACHE_POLICY_AIVIVT] = "AIVIVT",
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[ICACHE_POLICY_VIPT] = "VIPT",
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[ICACHE_POLICY_PIPT] = "PIPT",
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};
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unsigned long __icache_flags;
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static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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{
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unsigned int cpu = smp_processor_id();
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u32 l1ip = CTR_L1IP(info->reg_ctr);
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if (l1ip != ICACHE_POLICY_PIPT) {
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/*
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* VIPT caches are non-aliasing if the VA always equals the PA
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* in all bit positions that are covered by the index. This is
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* the case if the size of a way (# of sets * line size) does
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* not exceed PAGE_SIZE.
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*/
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u32 waysize = icache_get_numsets() * icache_get_linesize();
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if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
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set_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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if (l1ip == ICACHE_POLICY_AIVIVT)
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set_bit(ICACHEF_AIVIVT, &__icache_flags);
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pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
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}
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static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu)
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{
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if ((boot & mask) == (cur & mask))
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return 0;
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pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016lx, CPU%d: %#016lx\n",
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name, (unsigned long)boot, cpu, (unsigned long)cur);
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return 1;
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}
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#define CHECK_MASK(field, mask, boot, cur, cpu) \
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check_reg_mask(#field, mask, (boot)->reg_ ## field, (cur)->reg_ ## field, cpu)
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#define CHECK(field, boot, cur, cpu) \
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CHECK_MASK(field, ~0ULL, boot, cur, cpu)
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/*
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* Verify that CPUs don't have unexpected differences that will cause problems.
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*/
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static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
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{
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unsigned int cpu = smp_processor_id();
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struct cpuinfo_arm64 *boot = &boot_cpu_data;
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unsigned int diff = 0;
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/*
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* The kernel can handle differing I-cache policies, but otherwise
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* caches should look identical. Userspace JITs will make use of
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* *minLine.
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*/
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diff |= CHECK_MASK(ctr, 0xffff3fff, boot, cur, cpu);
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/*
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* Userspace may perform DC ZVA instructions. Mismatched block sizes
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* could result in too much or too little memory being zeroed if a
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* process is preempted and migrated between CPUs.
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*/
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diff |= CHECK(dczid, boot, cur, cpu);
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/* If different, timekeeping will be broken (especially with KVM) */
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diff |= CHECK(cntfrq, boot, cur, cpu);
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/*
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* The kernel uses self-hosted debug features and expects CPUs to
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* support identical debug features. We presently need CTX_CMPs, WRPs,
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* and BRPs to be identical.
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* ID_AA64DFR1 is currently RES0.
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*/
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diff |= CHECK(id_aa64dfr0, boot, cur, cpu);
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diff |= CHECK(id_aa64dfr1, boot, cur, cpu);
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/*
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* Even in big.LITTLE, processors should be identical instruction-set
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* wise.
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*/
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diff |= CHECK(id_aa64isar0, boot, cur, cpu);
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diff |= CHECK(id_aa64isar1, boot, cur, cpu);
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/*
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* Differing PARange support is fine as long as all peripherals and
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* memory are mapped within the minimum PARange of all CPUs.
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* Linux should not care about secure memory.
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* ID_AA64MMFR1 is currently RES0.
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*/
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diff |= CHECK_MASK(id_aa64mmfr0, 0xffffffffffff0ff0, boot, cur, cpu);
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diff |= CHECK(id_aa64mmfr1, boot, cur, cpu);
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/*
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* EL3 is not our concern.
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* ID_AA64PFR1 is currently RES0.
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*/
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diff |= CHECK_MASK(id_aa64pfr0, 0xffffffffffff0fff, boot, cur, cpu);
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diff |= CHECK(id_aa64pfr1, boot, cur, cpu);
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/*
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* If we have AArch32, we care about 32-bit features for compat. These
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* registers should be RES0 otherwise.
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*/
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diff |= CHECK(id_isar0, boot, cur, cpu);
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diff |= CHECK(id_isar1, boot, cur, cpu);
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diff |= CHECK(id_isar2, boot, cur, cpu);
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diff |= CHECK(id_isar3, boot, cur, cpu);
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diff |= CHECK(id_isar4, boot, cur, cpu);
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diff |= CHECK(id_isar5, boot, cur, cpu);
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/*
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* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
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* ACTLR formats could differ across CPUs and therefore would have to
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* be trapped for virtualization anyway.
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*/
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diff |= CHECK_MASK(id_mmfr0, 0xff0fffff, boot, cur, cpu);
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diff |= CHECK(id_mmfr1, boot, cur, cpu);
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diff |= CHECK(id_mmfr2, boot, cur, cpu);
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diff |= CHECK(id_mmfr3, boot, cur, cpu);
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diff |= CHECK(id_pfr0, boot, cur, cpu);
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diff |= CHECK(id_pfr1, boot, cur, cpu);
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/*
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* Mismatched CPU features are a recipe for disaster. Don't even
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* pretend to support them.
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*/
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WARN_TAINT_ONCE(diff, TAINT_CPU_OUT_OF_SPEC,
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"Unsupported CPU feature variation.\n");
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}
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static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
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{
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info->reg_cntfrq = arch_timer_get_cntfrq();
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info->reg_ctr = read_cpuid_cachetype();
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info->reg_dczid = read_cpuid(DCZID_EL0);
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info->reg_midr = read_cpuid_id();
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info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
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info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
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info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
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info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
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info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
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info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
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info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
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info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
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info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
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info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
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info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
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info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
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info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
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info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
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info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
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info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
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info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
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info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
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info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
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cpuinfo_detect_icache_policy(info);
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check_local_cpu_errata();
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}
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void cpuinfo_store_cpu(void)
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{
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struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
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__cpuinfo_store_cpu(info);
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cpuinfo_sanity_check(info);
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}
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void __init cpuinfo_store_boot_cpu(void)
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{
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struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
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__cpuinfo_store_cpu(info);
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boot_cpu_data = *info;
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}
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u64 __attribute_const__ icache_get_ccsidr(void)
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{
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u64 ccsidr;
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WARN_ON(preemptible());
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/* Select L1 I-cache and read its size ID register */
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asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"
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: "=r"(ccsidr) : "r"(1L));
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return ccsidr;
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}
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