![Zach Brown](/assets/img/avatar_default.png)
The sdhci controller on xilinx zynq devices will not function unless the CD bit is provided. http://www.xilinx.com/support/answers/61064.html In cases where it is impossible to provide the CD bit in hardware, setting the controller to test mode and then setting inserted to true will get the controller to function without the CD bit. When the device has the property xlnx,fails-without-test-cd the driver changes the controller to test mode and sets test inserted to true to make the controller function. Signed-off-by: Zach Brown <zach.brown@ni.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
724 lines
21 KiB
C
724 lines
21 KiB
C
/*
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* Arasan Secure Digital Host Controller Interface.
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* Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2012 Wind River Systems, Inc.
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* Copyright (C) 2013 Pengutronix e.K.
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* Copyright (C) 2013 Xilinx Inc.
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*
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* Based on sdhci-of-esdhc.c
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include "sdhci-pltfm.h"
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#include <linux/of.h>
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#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
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#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
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#define VENDOR_ENHANCED_STROBE BIT(0)
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#define CLK_CTRL_TIMEOUT_SHIFT 16
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#define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
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#define CLK_CTRL_TIMEOUT_MIN_EXP 13
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#define PHY_CLK_TOO_SLOW_HZ 400000
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/*
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* On some SoCs the syscon area has a feature where the upper 16-bits of
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* each 32-bit register act as a write mask for the lower 16-bits. This allows
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* atomic updates of the register without locking. This macro is used on SoCs
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* that have that feature.
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*/
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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/**
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* struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
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*
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* @reg: Offset within the syscon of the register containing this field
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* @width: Number of bits for this field
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* @shift: Bit offset within @reg of this field (or -1 if not avail)
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*/
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struct sdhci_arasan_soc_ctl_field {
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u32 reg;
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u16 width;
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s16 shift;
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};
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/**
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* struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
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*
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* It's up to the licensee of the Arsan IP block to make these available
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* somewhere if needed. Presumably these will be scattered somewhere that's
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* accessible via the syscon API.
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*
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* @baseclkfreq: Where to find corecfg_baseclkfreq
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* @clockmultiplier: Where to find corecfg_clockmultiplier
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* @hiword_update: If true, use HIWORD_UPDATE to access the syscon
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*/
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struct sdhci_arasan_soc_ctl_map {
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struct sdhci_arasan_soc_ctl_field baseclkfreq;
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struct sdhci_arasan_soc_ctl_field clockmultiplier;
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bool hiword_update;
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};
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/**
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* struct sdhci_arasan_data
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* @host: Pointer to the main SDHCI host structure.
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* @clk_ahb: Pointer to the AHB clock
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* @phy: Pointer to the generic phy
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* @is_phy_on: True if the PHY is on; false if not.
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* @sdcardclk_hw: Struct for the clock we might provide to a PHY.
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* @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
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* @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
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* @soc_ctl_map: Map to get offsets into soc_ctl registers.
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*/
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struct sdhci_arasan_data {
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struct sdhci_host *host;
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struct clk *clk_ahb;
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struct phy *phy;
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bool is_phy_on;
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struct clk_hw sdcardclk_hw;
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struct clk *sdcardclk;
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struct regmap *soc_ctl_base;
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const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
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unsigned int quirks; /* Arasan deviations from spec */
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/* Controller does not have CD wired and will not function normally without */
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#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
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};
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static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
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.baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
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.clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
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.hiword_update = true,
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};
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/**
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* sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
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*
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* This function allows writing to fields in sdhci_arasan_soc_ctl_map.
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* Note that if a field is specified as not available (shift < 0) then
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* this function will silently return an error code. It will be noisy
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* and print errors for any other (unexpected) errors.
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*
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* @host: The sdhci_host
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* @fld: The field to write to
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* @val: The value to write
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*/
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static int sdhci_arasan_syscon_write(struct sdhci_host *host,
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const struct sdhci_arasan_soc_ctl_field *fld,
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u32 val)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
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u32 reg = fld->reg;
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u16 width = fld->width;
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s16 shift = fld->shift;
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int ret;
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/*
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* Silently return errors for shift < 0 so caller doesn't have
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* to check for fields which are optional. For fields that
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* are required then caller needs to do something special
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* anyway.
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*/
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if (shift < 0)
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return -EINVAL;
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if (sdhci_arasan->soc_ctl_map->hiword_update)
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ret = regmap_write(soc_ctl_base, reg,
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HIWORD_UPDATE(val, GENMASK(width, 0),
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shift));
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else
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ret = regmap_update_bits(soc_ctl_base, reg,
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GENMASK(shift + width, shift),
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val << shift);
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/* Yell about (unexpected) regmap errors */
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if (ret)
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pr_warn("%s: Regmap write fail: %d\n",
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mmc_hostname(host->mmc), ret);
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return ret;
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}
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static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
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{
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u32 div;
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unsigned long freq;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
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div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
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freq = clk_get_rate(pltfm_host->clk);
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freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
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return freq;
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}
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static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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bool ctrl_phy = false;
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if (!IS_ERR(sdhci_arasan->phy)) {
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if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
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/*
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* If PHY off, set clock to max speed and power PHY on.
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*
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* Although PHY docs apparently suggest power cycling
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* when changing the clock the PHY doesn't like to be
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* powered on while at low speeds like those used in ID
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* mode. Even worse is powering the PHY on while the
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* clock is off.
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*
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* To workaround the PHY limitations, the best we can
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* do is to power it on at a faster speed and then slam
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* through low speeds without power cycling.
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*/
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sdhci_set_clock(host, host->max_clk);
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spin_unlock_irq(&host->lock);
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phy_power_on(sdhci_arasan->phy);
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spin_lock_irq(&host->lock);
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sdhci_arasan->is_phy_on = true;
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/*
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* We'll now fall through to the below case with
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* ctrl_phy = false (so we won't turn off/on). The
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* sdhci_set_clock() will set the real clock.
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*/
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} else if (clock > PHY_CLK_TOO_SLOW_HZ) {
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/*
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* At higher clock speeds the PHY is fine being power
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* cycled and docs say you _should_ power cycle when
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* changing clock speeds.
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*/
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ctrl_phy = true;
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}
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}
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if (ctrl_phy && sdhci_arasan->is_phy_on) {
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spin_unlock_irq(&host->lock);
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phy_power_off(sdhci_arasan->phy);
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spin_lock_irq(&host->lock);
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sdhci_arasan->is_phy_on = false;
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}
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sdhci_set_clock(host, clock);
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if (ctrl_phy) {
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spin_unlock_irq(&host->lock);
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phy_power_on(sdhci_arasan->phy);
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spin_lock_irq(&host->lock);
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sdhci_arasan->is_phy_on = true;
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}
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}
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static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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u32 vendor;
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struct sdhci_host *host = mmc_priv(mmc);
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vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
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if (ios->enhanced_strobe)
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vendor |= VENDOR_ENHANCED_STROBE;
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else
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vendor &= ~VENDOR_ENHANCED_STROBE;
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writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
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}
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void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
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{
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u8 ctrl;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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sdhci_reset(host, mask);
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if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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}
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static struct sdhci_ops sdhci_arasan_ops = {
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.set_clock = sdhci_arasan_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.get_timeout_clock = sdhci_arasan_get_timeout_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_arasan_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static struct sdhci_pltfm_data sdhci_arasan_pdata = {
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.ops = &sdhci_arasan_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
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};
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#ifdef CONFIG_PM_SLEEP
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/**
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* sdhci_arasan_suspend - Suspend method for the driver
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* @dev: Address of the device structure
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* Returns 0 on success and error value on error
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*
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* Put the device in a low power state.
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*/
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static int sdhci_arasan_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = sdhci_suspend_host(host);
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if (ret)
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return ret;
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if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
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ret = phy_power_off(sdhci_arasan->phy);
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if (ret) {
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dev_err(dev, "Cannot power off phy.\n");
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sdhci_resume_host(host);
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return ret;
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}
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sdhci_arasan->is_phy_on = false;
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}
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clk_disable(pltfm_host->clk);
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clk_disable(sdhci_arasan->clk_ahb);
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return 0;
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}
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/**
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* sdhci_arasan_resume - Resume method for the driver
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* @dev: Address of the device structure
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* Returns 0 on success and error value on error
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*
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* Resume operation after suspend
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*/
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static int sdhci_arasan_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = clk_enable(sdhci_arasan->clk_ahb);
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if (ret) {
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dev_err(dev, "Cannot enable AHB clock.\n");
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return ret;
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}
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ret = clk_enable(pltfm_host->clk);
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if (ret) {
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dev_err(dev, "Cannot enable SD clock.\n");
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return ret;
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}
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if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
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ret = phy_power_on(sdhci_arasan->phy);
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if (ret) {
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dev_err(dev, "Cannot power on phy.\n");
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return ret;
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}
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sdhci_arasan->is_phy_on = true;
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}
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return sdhci_resume_host(host);
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}
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#endif /* ! CONFIG_PM_SLEEP */
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static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
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sdhci_arasan_resume);
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static const struct of_device_id sdhci_arasan_of_match[] = {
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/* SoC-specific compatible strings w/ soc_ctl_map */
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{
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.compatible = "rockchip,rk3399-sdhci-5.1",
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.data = &rk3399_soc_ctl_map,
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},
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/* Generic compatible below here */
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{ .compatible = "arasan,sdhci-8.9a" },
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{ .compatible = "arasan,sdhci-5.1" },
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{ .compatible = "arasan,sdhci-4.9a" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
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/**
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* sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
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*
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* Return the current actual rate of the SD card clock. This can be used
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* to communicate with out PHY.
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*
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* @hw: Pointer to the hardware clock structure.
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* @parent_rate The parent rate (should be rate of clk_xin).
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* Returns the card clock rate.
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*/
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static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sdhci_arasan_data *sdhci_arasan =
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container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
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struct sdhci_host *host = sdhci_arasan->host;
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return host->mmc->actual_clock;
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}
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static const struct clk_ops arasan_sdcardclk_ops = {
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.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
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};
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/**
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* sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
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*
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* The corecfg_clockmultiplier is supposed to contain clock multiplier
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* value of programmable clock generator.
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*
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* NOTES:
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* - Many existing devices don't seem to do this and work fine. To keep
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* compatibility for old hardware where the device tree doesn't provide a
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* register map, this function is a noop if a soc_ctl_map hasn't been provided
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* for this platform.
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* - The value of corecfg_clockmultiplier should sync with that of corresponding
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* value reading from sdhci_capability_register. So this function is called
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* once at probe time and never called again.
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*
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* @host: The sdhci_host
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*/
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static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
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u32 value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
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sdhci_arasan->soc_ctl_map;
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/* Having a map is optional */
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if (!soc_ctl_map)
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return;
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/* If we have a map, we expect to have a syscon */
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if (!sdhci_arasan->soc_ctl_base) {
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pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
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mmc_hostname(host->mmc));
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return;
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}
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sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
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}
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/**
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* sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
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*
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* The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
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* function can be used to make that happen.
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*
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* NOTES:
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* - Many existing devices don't seem to do this and work fine. To keep
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* compatibility for old hardware where the device tree doesn't provide a
|
|
* register map, this function is a noop if a soc_ctl_map hasn't been provided
|
|
* for this platform.
|
|
* - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
|
|
* to achieve lower clock rates. That means that this function is called once
|
|
* at probe time and never called again.
|
|
*
|
|
* @host: The sdhci_host
|
|
*/
|
|
static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
|
|
const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
|
|
sdhci_arasan->soc_ctl_map;
|
|
u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
|
|
|
|
/* Having a map is optional */
|
|
if (!soc_ctl_map)
|
|
return;
|
|
|
|
/* If we have a map, we expect to have a syscon */
|
|
if (!sdhci_arasan->soc_ctl_base) {
|
|
pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
|
|
mmc_hostname(host->mmc));
|
|
return;
|
|
}
|
|
|
|
sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
|
|
}
|
|
|
|
/**
|
|
* sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
|
|
*
|
|
* Some PHY devices need to know what the actual card clock is. In order for
|
|
* them to find out, we'll provide a clock through the common clock framework
|
|
* for them to query.
|
|
*
|
|
* Note: without seriously re-architecting SDHCI's clock code and testing on
|
|
* all platforms, there's no way to create a totally beautiful clock here
|
|
* with all clock ops implemented. Instead, we'll just create a clock that can
|
|
* be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
|
|
* framework that we're doing things behind its back. This should be sufficient
|
|
* to create nice clean device tree bindings and later (if needed) we can try
|
|
* re-architecting SDHCI if we see some benefit to it.
|
|
*
|
|
* @sdhci_arasan: Our private data structure.
|
|
* @clk_xin: Pointer to the functional clock
|
|
* @dev: Pointer to our struct device.
|
|
* Returns 0 on success and error value on error
|
|
*/
|
|
static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
|
|
struct clk *clk_xin,
|
|
struct device *dev)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
struct clk_init_data sdcardclk_init;
|
|
const char *parent_clk_name;
|
|
int ret;
|
|
|
|
/* Providing a clock to the PHY is optional; no error if missing */
|
|
if (!of_find_property(np, "#clock-cells", NULL))
|
|
return 0;
|
|
|
|
ret = of_property_read_string_index(np, "clock-output-names", 0,
|
|
&sdcardclk_init.name);
|
|
if (ret) {
|
|
dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
|
|
return ret;
|
|
}
|
|
|
|
parent_clk_name = __clk_get_name(clk_xin);
|
|
sdcardclk_init.parent_names = &parent_clk_name;
|
|
sdcardclk_init.num_parents = 1;
|
|
sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
|
|
sdcardclk_init.ops = &arasan_sdcardclk_ops;
|
|
|
|
sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
|
|
sdhci_arasan->sdcardclk =
|
|
devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
|
|
sdhci_arasan->sdcardclk_hw.init = NULL;
|
|
|
|
ret = of_clk_add_provider(np, of_clk_src_simple_get,
|
|
sdhci_arasan->sdcardclk);
|
|
if (ret)
|
|
dev_err(dev, "Failed to add clock provider\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
|
|
*
|
|
* Should be called any time we're exiting and sdhci_arasan_register_sdclk()
|
|
* returned success.
|
|
*
|
|
* @dev: Pointer to our struct device.
|
|
*/
|
|
static void sdhci_arasan_unregister_sdclk(struct device *dev)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
|
|
if (!of_find_property(np, "#clock-cells", NULL))
|
|
return;
|
|
|
|
of_clk_del_provider(dev->of_node);
|
|
}
|
|
|
|
static int sdhci_arasan_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
const struct of_device_id *match;
|
|
struct device_node *node;
|
|
struct clk *clk_xin;
|
|
struct sdhci_host *host;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_arasan_data *sdhci_arasan;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
|
|
sizeof(*sdhci_arasan));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
|
|
sdhci_arasan->host = host;
|
|
|
|
match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
|
|
sdhci_arasan->soc_ctl_map = match->data;
|
|
|
|
node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
|
|
if (node) {
|
|
sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
|
|
of_node_put(node);
|
|
|
|
if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
|
|
ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev, "Can't get syscon: %d\n",
|
|
ret);
|
|
goto err_pltfm_free;
|
|
}
|
|
}
|
|
|
|
sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
|
|
if (IS_ERR(sdhci_arasan->clk_ahb)) {
|
|
dev_err(&pdev->dev, "clk_ahb clock not found.\n");
|
|
ret = PTR_ERR(sdhci_arasan->clk_ahb);
|
|
goto err_pltfm_free;
|
|
}
|
|
|
|
clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
|
|
if (IS_ERR(clk_xin)) {
|
|
dev_err(&pdev->dev, "clk_xin clock not found.\n");
|
|
ret = PTR_ERR(clk_xin);
|
|
goto err_pltfm_free;
|
|
}
|
|
|
|
ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
|
|
goto err_pltfm_free;
|
|
}
|
|
|
|
ret = clk_prepare_enable(clk_xin);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to enable SD clock.\n");
|
|
goto clk_dis_ahb;
|
|
}
|
|
|
|
sdhci_get_of_property(pdev);
|
|
|
|
if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
|
|
sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
|
|
|
|
pltfm_host->clk = clk_xin;
|
|
|
|
if (of_device_is_compatible(pdev->dev.of_node,
|
|
"rockchip,rk3399-sdhci-5.1"))
|
|
sdhci_arasan_update_clockmultiplier(host, 0x0);
|
|
|
|
sdhci_arasan_update_baseclkfreq(host);
|
|
|
|
ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
|
|
if (ret)
|
|
goto clk_disable_all;
|
|
|
|
ret = mmc_of_parse(host->mmc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
|
|
goto unreg_clk;
|
|
}
|
|
|
|
sdhci_arasan->phy = ERR_PTR(-ENODEV);
|
|
if (of_device_is_compatible(pdev->dev.of_node,
|
|
"arasan,sdhci-5.1")) {
|
|
sdhci_arasan->phy = devm_phy_get(&pdev->dev,
|
|
"phy_arasan");
|
|
if (IS_ERR(sdhci_arasan->phy)) {
|
|
ret = PTR_ERR(sdhci_arasan->phy);
|
|
dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
|
|
goto unreg_clk;
|
|
}
|
|
|
|
ret = phy_init(sdhci_arasan->phy);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "phy_init err.\n");
|
|
goto unreg_clk;
|
|
}
|
|
|
|
host->mmc_host_ops.hs400_enhanced_strobe =
|
|
sdhci_arasan_hs400_enhanced_strobe;
|
|
}
|
|
|
|
ret = sdhci_add_host(host);
|
|
if (ret)
|
|
goto err_add_host;
|
|
|
|
return 0;
|
|
|
|
err_add_host:
|
|
if (!IS_ERR(sdhci_arasan->phy))
|
|
phy_exit(sdhci_arasan->phy);
|
|
unreg_clk:
|
|
sdhci_arasan_unregister_sdclk(&pdev->dev);
|
|
clk_disable_all:
|
|
clk_disable_unprepare(clk_xin);
|
|
clk_dis_ahb:
|
|
clk_disable_unprepare(sdhci_arasan->clk_ahb);
|
|
err_pltfm_free:
|
|
sdhci_pltfm_free(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_arasan_remove(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
|
|
struct clk *clk_ahb = sdhci_arasan->clk_ahb;
|
|
|
|
if (!IS_ERR(sdhci_arasan->phy)) {
|
|
if (sdhci_arasan->is_phy_on)
|
|
phy_power_off(sdhci_arasan->phy);
|
|
phy_exit(sdhci_arasan->phy);
|
|
}
|
|
|
|
sdhci_arasan_unregister_sdclk(&pdev->dev);
|
|
|
|
ret = sdhci_pltfm_unregister(pdev);
|
|
|
|
clk_disable_unprepare(clk_ahb);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver sdhci_arasan_driver = {
|
|
.driver = {
|
|
.name = "sdhci-arasan",
|
|
.of_match_table = sdhci_arasan_of_match,
|
|
.pm = &sdhci_arasan_dev_pm_ops,
|
|
},
|
|
.probe = sdhci_arasan_probe,
|
|
.remove = sdhci_arasan_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_arasan_driver);
|
|
|
|
MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
|
|
MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
|
|
MODULE_LICENSE("GPL");
|