![Jaehoon Chung](/assets/img/avatar_default.png)
In linux/mmc/host.h, mmc_card_is_removable() is already defined. It should be maintainted more easier than now. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
351 lines
10 KiB
C
351 lines
10 KiB
C
/*
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* Atmel SDMMC controller driver.
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include "sdhci-pltfm.h"
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#define SDMMC_CACR 0x230
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#define SDMMC_CACR_CAPWREN BIT(0)
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#define SDMMC_CACR_KEY (0x46 << 8)
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#define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
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struct sdhci_at91_priv {
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struct clk *hclock;
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struct clk *gck;
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struct clk *mainck;
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};
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static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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u16 clk;
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unsigned long timeout;
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host->mmc->actual_clock = 0;
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/*
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* There is no requirement to disable the internal clock before
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* changing the SD clock configuration. Moreover, disabling the
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* internal clock, changing the configuration and re-enabling the
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* internal clock causes some bugs. It can prevent to get the internal
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* clock stable flag ready and an unexpected switch to the base clock
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* when using presets.
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*/
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return;
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clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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clk |= SDHCI_CLOCK_INT_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Wait max 20 ms */
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timeout = 20;
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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pr_err("%s: Internal clock never stabilised.\n",
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mmc_hostname(host->mmc));
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return;
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}
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timeout--;
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mdelay(1);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
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.set_clock = sdhci_at91_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data soc_data_sama5d2 = {
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.ops = &sdhci_at91_sama5d2_ops,
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};
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static const struct of_device_id sdhci_at91_dt_match[] = {
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{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
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{}
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};
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#ifdef CONFIG_PM
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static int sdhci_at91_runtime_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = sdhci_runtime_suspend_host(host);
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clk_disable_unprepare(priv->gck);
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clk_disable_unprepare(priv->hclock);
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clk_disable_unprepare(priv->mainck);
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return ret;
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}
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static int sdhci_at91_runtime_resume(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = clk_prepare_enable(priv->mainck);
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if (ret) {
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dev_err(dev, "can't enable mainck\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->hclock);
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if (ret) {
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dev_err(dev, "can't enable hclock\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->gck);
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if (ret) {
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dev_err(dev, "can't enable gck\n");
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return ret;
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}
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return sdhci_runtime_resume_host(host);
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}
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#endif /* CONFIG_PM */
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static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
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sdhci_at91_runtime_resume,
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NULL)
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};
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static int sdhci_at91_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct sdhci_pltfm_data *soc_data;
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_at91_priv *priv;
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unsigned int caps0, caps1;
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unsigned int clk_base, clk_mul;
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unsigned int gck_rate, real_gck_rate;
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int ret;
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unsigned int preset_div;
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match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
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if (!match)
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return -EINVAL;
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soc_data = match->data;
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host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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priv = sdhci_pltfm_priv(pltfm_host);
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priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
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if (IS_ERR(priv->mainck)) {
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dev_err(&pdev->dev, "failed to get baseclk\n");
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return PTR_ERR(priv->mainck);
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}
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priv->hclock = devm_clk_get(&pdev->dev, "hclock");
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if (IS_ERR(priv->hclock)) {
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dev_err(&pdev->dev, "failed to get hclock\n");
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return PTR_ERR(priv->hclock);
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}
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priv->gck = devm_clk_get(&pdev->dev, "multclk");
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if (IS_ERR(priv->gck)) {
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dev_err(&pdev->dev, "failed to get multclk\n");
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return PTR_ERR(priv->gck);
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}
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/*
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* The mult clock is provided by as a generated clock by the PMC
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* controller. In order to set the rate of gck, we have to get the
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* base clock rate and the clock mult from capabilities.
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*/
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clk_prepare_enable(priv->hclock);
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caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
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caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
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clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
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clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
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gck_rate = clk_base * 1000000 * (clk_mul + 1);
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ret = clk_set_rate(priv->gck, gck_rate);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to set gck");
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goto hclock_disable_unprepare;
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}
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/*
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* We need to check if we have the requested rate for gck because in
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* some cases this rate could be not supported. If it happens, the rate
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* is the closest one gck can provide. We have to update the value
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* of clk mul.
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*/
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real_gck_rate = clk_get_rate(priv->gck);
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if (real_gck_rate != gck_rate) {
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clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
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caps1 &= (~SDHCI_CLOCK_MUL_MASK);
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caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
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/* Set capabilities in r/w mode. */
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writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
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writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
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/* Set capabilities in ro mode. */
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writel(0, host->ioaddr + SDMMC_CACR);
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dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
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clk_mul, real_gck_rate);
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}
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/*
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* We have to set preset values because it depends on the clk_mul
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* value. Moreover, SDR104 is supported in a degraded mode since the
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* maximum sd clock value is 120 MHz instead of 208 MHz. For that
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* reason, we need to use presets to support SDR104.
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*/
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preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR12);
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preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR25);
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preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR50);
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preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_SDR104);
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preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
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writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
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host->ioaddr + SDHCI_PRESET_FOR_DDR50);
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clk_prepare_enable(priv->mainck);
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clk_prepare_enable(priv->gck);
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto clocks_disable_unprepare;
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sdhci_get_of_property(pdev);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
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pm_runtime_use_autosuspend(&pdev->dev);
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ret = sdhci_add_host(host);
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if (ret)
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goto pm_runtime_disable;
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/*
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* When calling sdhci_runtime_suspend_host(), the sdhci layer makes
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* the assumption that all the clocks of the controller are disabled.
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* It means we can't get irq from it when it is runtime suspended.
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* For that reason, it is not planned to wake-up on a card detect irq
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* from the controller.
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* If we want to use runtime PM and to be able to wake-up on card
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* insertion, we have to use a GPIO for the card detection or we can
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* use polling. Be aware that using polling will resume/suspend the
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* controller between each attempt.
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* Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
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* to enable polling via device tree with broken-cd property.
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*/
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if (mmc_card_is_removable(host->mmc) &&
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mmc_gpio_get_cd(host->mmc) < 0) {
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host->mmc->caps |= MMC_CAP_NEEDS_POLL;
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host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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}
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pm_runtime_put_autosuspend(&pdev->dev);
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return 0;
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pm_runtime_disable:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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clocks_disable_unprepare:
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clk_disable_unprepare(priv->gck);
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clk_disable_unprepare(priv->mainck);
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hclock_disable_unprepare:
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clk_disable_unprepare(priv->hclock);
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static int sdhci_at91_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct clk *gck = priv->gck;
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struct clk *hclock = priv->hclock;
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struct clk *mainck = priv->mainck;
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pm_runtime_get_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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sdhci_pltfm_unregister(pdev);
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clk_disable_unprepare(gck);
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clk_disable_unprepare(hclock);
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clk_disable_unprepare(mainck);
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return 0;
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}
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static struct platform_driver sdhci_at91_driver = {
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.driver = {
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.name = "sdhci-at91",
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.of_match_table = sdhci_at91_dt_match,
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.pm = &sdhci_at91_dev_pm_ops,
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},
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.probe = sdhci_at91_probe,
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.remove = sdhci_at91_remove,
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};
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module_platform_driver(sdhci_at91_driver);
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MODULE_DESCRIPTION("SDHCI driver for at91");
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MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
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MODULE_LICENSE("GPL v2");
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