![Julia Lawall](/assets/img/avatar_default.png)
Use of_property_read_bool to check for the existence of a property. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e1,e2; statement S2,S1; @@ - if (of_get_property(e1,e2,NULL)) + if (of_property_read_bool(e1,e2)) S1 else S2 // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
668 lines
17 KiB
C
668 lines
17 KiB
C
/*
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* Freescale eSDHC controller driver.
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*
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* Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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*
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* Authors: Xiaobo Xie <X.Xie@freescale.com>
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#define VENDOR_V_22 0x12
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#define VENDOR_V_23 0x13
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struct sdhci_esdhc {
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u8 vendor_ver;
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u8 spec_ver;
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};
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/**
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* esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
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* to make it compatible with SD spec.
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*
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* @host: pointer to sdhci_host
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* @spec_reg: SD spec register address
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* @value: 32bit eSDHC register value on spec_reg address
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*
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* In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
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* registers are 32 bits. There are differences in register size, register
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* address, register function, bit position and function between eSDHC spec
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* and SD spec.
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*
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* Return a fixed up register value
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*/
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static u32 esdhc_readl_fixup(struct sdhci_host *host,
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int spec_reg, u32 value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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u32 ret;
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/*
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* The bit of ADMA flag in eSDHC is not compatible with standard
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* SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
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* supported by eSDHC.
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* And for many FSL eSDHC controller, the reset value of field
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* SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
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* only these vendor version is greater than 2.2/0x12 support ADMA.
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*/
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if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
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if (esdhc->vendor_ver > VENDOR_V_22) {
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ret = value | SDHCI_CAN_DO_ADMA2;
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return ret;
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}
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}
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ret = value;
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return ret;
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}
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static u16 esdhc_readw_fixup(struct sdhci_host *host,
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int spec_reg, u32 value)
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{
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u16 ret;
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int shift = (spec_reg & 0x2) * 8;
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if (spec_reg == SDHCI_HOST_VERSION)
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ret = value & 0xffff;
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else
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ret = (value >> shift) & 0xffff;
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return ret;
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}
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static u8 esdhc_readb_fixup(struct sdhci_host *host,
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int spec_reg, u32 value)
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{
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u8 ret;
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u8 dma_bits;
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int shift = (spec_reg & 0x3) * 8;
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ret = (value >> shift) & 0xff;
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/*
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* "DMA select" locates at offset 0x28 in SD specification, but on
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* P5020 or P3041, it locates at 0x29.
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*/
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if (spec_reg == SDHCI_HOST_CONTROL) {
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
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/* fixup the result */
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ret &= ~SDHCI_CTRL_DMA_MASK;
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ret |= dma_bits;
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}
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return ret;
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}
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/**
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* esdhc_write*_fixup - Fixup the SD spec register value so that it could be
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* written into eSDHC register.
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*
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* @host: pointer to sdhci_host
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* @spec_reg: SD spec register address
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* @value: 8/16/32bit SD spec register value that would be written
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* @old_value: 32bit eSDHC register value on spec_reg address
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*
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* In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
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* registers are 32 bits. There are differences in register size, register
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* address, register function, bit position and function between eSDHC spec
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* and SD spec.
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*
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* Return a fixed up register value
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*/
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static u32 esdhc_writel_fixup(struct sdhci_host *host,
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int spec_reg, u32 value, u32 old_value)
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{
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u32 ret;
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/*
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* Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
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* when SYSCTL[RSTD] is set for some special operations.
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* No any impact on other operation.
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*/
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if (spec_reg == SDHCI_INT_ENABLE)
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ret = value | SDHCI_INT_BLK_GAP;
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else
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ret = value;
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return ret;
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}
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static u32 esdhc_writew_fixup(struct sdhci_host *host,
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int spec_reg, u16 value, u32 old_value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int shift = (spec_reg & 0x2) * 8;
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u32 ret;
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switch (spec_reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below. Return old value.
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*/
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pltfm_host->xfer_mode_shadow = value;
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return old_value;
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case SDHCI_COMMAND:
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ret = (value << 16) | pltfm_host->xfer_mode_shadow;
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return ret;
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}
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ret = old_value & (~(0xffff << shift));
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ret |= (value << shift);
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if (spec_reg == SDHCI_BLOCK_SIZE) {
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/*
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* Two last DMA bits are reserved, and first one is used for
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* non-standard blksz of 4096 bytes that we don't support
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* yet. So clear the DMA boundary bits.
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*/
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ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
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}
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return ret;
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}
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static u32 esdhc_writeb_fixup(struct sdhci_host *host,
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int spec_reg, u8 value, u32 old_value)
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{
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u32 ret;
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u32 dma_bits;
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u8 tmp;
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int shift = (spec_reg & 0x3) * 8;
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/*
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* eSDHC doesn't have a standard power control register, so we do
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* nothing here to avoid incorrect operation.
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*/
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if (spec_reg == SDHCI_POWER_CONTROL)
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return old_value;
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/*
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* "DMA select" location is offset 0x28 in SD specification, but on
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* P5020 or P3041, it's located at 0x29.
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*/
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if (spec_reg == SDHCI_HOST_CONTROL) {
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/*
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* If host control register is not standard, exit
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* this function
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*/
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if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
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return old_value;
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/* DMA select is 22,23 bits in Protocol Control Register */
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dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
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ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
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tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
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(old_value & SDHCI_CTRL_DMA_MASK);
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ret = (ret & (~0xff)) | tmp;
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/* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
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ret &= ~ESDHC_HOST_CONTROL_RES;
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return ret;
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}
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ret = (old_value & (~(0xff << shift))) | (value << shift);
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return ret;
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}
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static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
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{
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u32 ret;
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u32 value;
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value = ioread32be(host->ioaddr + reg);
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ret = esdhc_readl_fixup(host, reg, value);
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return ret;
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}
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static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
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{
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u32 ret;
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u32 value;
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value = ioread32(host->ioaddr + reg);
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ret = esdhc_readl_fixup(host, reg, value);
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return ret;
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}
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static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_readw_fixup(host, reg, value);
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return ret;
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}
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static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
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{
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u16 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_readw_fixup(host, reg, value);
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return ret;
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}
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static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
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{
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u8 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_readb_fixup(host, reg, value);
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return ret;
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}
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static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
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{
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u8 ret;
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u32 value;
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int base = reg & ~0x3;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_readb_fixup(host, reg, value);
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return ret;
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}
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static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
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{
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u32 value;
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value = esdhc_writel_fixup(host, reg, val, 0);
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iowrite32be(value, host->ioaddr + reg);
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}
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static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
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{
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u32 value;
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value = esdhc_writel_fixup(host, reg, val, 0);
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iowrite32(value, host->ioaddr + reg);
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}
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static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_writew_fixup(host, reg, val, value);
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if (reg != SDHCI_TRANSFER_MODE)
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iowrite32be(ret, host->ioaddr + base);
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}
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static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_writew_fixup(host, reg, val, value);
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if (reg != SDHCI_TRANSFER_MODE)
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iowrite32(ret, host->ioaddr + base);
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}
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static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32be(host->ioaddr + base);
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ret = esdhc_writeb_fixup(host, reg, val, value);
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iowrite32be(ret, host->ioaddr + base);
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}
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static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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u32 value;
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u32 ret;
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value = ioread32(host->ioaddr + base);
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ret = esdhc_writeb_fixup(host, reg, val, value);
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iowrite32(ret, host->ioaddr + base);
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}
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/*
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* For Abort or Suspend after Stop at Block Gap, ignore the ADMA
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* error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
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* and Block Gap Event(IRQSTAT[BGE]) are also set.
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* For Continue, apply soft reset for data(SYSCTL[RSTD]);
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* and re-issue the entire read transaction from beginning.
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*/
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static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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bool applicable;
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dma_addr_t dmastart;
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dma_addr_t dmanow;
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applicable = (intmask & SDHCI_INT_DATA_END) &&
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(intmask & SDHCI_INT_BLK_GAP) &&
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(esdhc->vendor_ver == VENDOR_V_23);
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if (!applicable)
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return;
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host->data->error = 0;
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dmastart = sg_dma_address(host->data->sg);
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dmanow = dmastart + host->data->bytes_xfered;
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/*
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* Force update to the next DMA block boundary.
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*/
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dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
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SDHCI_DEFAULT_BOUNDARY_SIZE;
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host->data->bytes_xfered = dmanow - dmastart;
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sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
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}
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static int esdhc_of_enable_dma(struct sdhci_host *host)
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{
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u32 value;
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value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
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value |= ESDHC_DMA_SNOOP;
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sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
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return 0;
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}
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static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return pltfm_host->clock;
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}
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static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return pltfm_host->clock / 256 / 16;
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}
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static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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int pre_div = 1;
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int div = 1;
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u32 temp;
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host->mmc->actual_clock = 0;
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if (clock == 0)
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return;
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/* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
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if (esdhc->vendor_ver < VENDOR_V_23)
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pre_div = 2;
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/* Workaround to reduce the clock frequency for p1010 esdhc */
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if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
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if (clock > 20000000)
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clock -= 5000000;
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if (clock > 40000000)
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clock -= 5000000;
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}
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
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| ESDHC_CLOCK_MASK);
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sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
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while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
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pre_div *= 2;
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while (host->max_clk / pre_div / div > clock && div < 16)
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div++;
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->max_clk / pre_div / div);
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host->mmc->actual_clock = host->max_clk / pre_div / div;
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pre_div >>= 1;
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div--;
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
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| (div << ESDHC_DIVIDER_SHIFT)
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| (pre_div << ESDHC_PREDIV_SHIFT));
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sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
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mdelay(1);
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}
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static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
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{
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u32 ctrl;
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ctrl = sdhci_readl(host, ESDHC_PROCTL);
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ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
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switch (width) {
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case MMC_BUS_WIDTH_8:
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ctrl |= ESDHC_CTRL_8BITBUS;
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break;
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case MMC_BUS_WIDTH_4:
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ctrl |= ESDHC_CTRL_4BITBUS;
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break;
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default:
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break;
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}
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sdhci_writel(host, ctrl, ESDHC_PROCTL);
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}
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static void esdhc_reset(struct sdhci_host *host, u8 mask)
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{
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sdhci_reset(host, mask);
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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}
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#ifdef CONFIG_PM_SLEEP
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static u32 esdhc_proctl;
|
|
static int esdhc_of_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
|
|
|
|
return sdhci_suspend_host(host);
|
|
}
|
|
|
|
static int esdhc_of_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
int ret = sdhci_resume_host(host);
|
|
|
|
if (ret == 0) {
|
|
/* Isn't this already done by sdhci_resume_host() ? --rmk */
|
|
esdhc_of_enable_dma(host);
|
|
sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
|
|
}
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
|
|
esdhc_of_suspend,
|
|
esdhc_of_resume);
|
|
|
|
static const struct sdhci_ops sdhci_esdhc_be_ops = {
|
|
.read_l = esdhc_be_readl,
|
|
.read_w = esdhc_be_readw,
|
|
.read_b = esdhc_be_readb,
|
|
.write_l = esdhc_be_writel,
|
|
.write_w = esdhc_be_writew,
|
|
.write_b = esdhc_be_writeb,
|
|
.set_clock = esdhc_of_set_clock,
|
|
.enable_dma = esdhc_of_enable_dma,
|
|
.get_max_clock = esdhc_of_get_max_clock,
|
|
.get_min_clock = esdhc_of_get_min_clock,
|
|
.adma_workaround = esdhc_of_adma_workaround,
|
|
.set_bus_width = esdhc_pltfm_set_bus_width,
|
|
.reset = esdhc_reset,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
};
|
|
|
|
static const struct sdhci_ops sdhci_esdhc_le_ops = {
|
|
.read_l = esdhc_le_readl,
|
|
.read_w = esdhc_le_readw,
|
|
.read_b = esdhc_le_readb,
|
|
.write_l = esdhc_le_writel,
|
|
.write_w = esdhc_le_writew,
|
|
.write_b = esdhc_le_writeb,
|
|
.set_clock = esdhc_of_set_clock,
|
|
.enable_dma = esdhc_of_enable_dma,
|
|
.get_max_clock = esdhc_of_get_max_clock,
|
|
.get_min_clock = esdhc_of_get_min_clock,
|
|
.adma_workaround = esdhc_of_adma_workaround,
|
|
.set_bus_width = esdhc_pltfm_set_bus_width,
|
|
.reset = esdhc_reset,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
|
|
.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
|
| SDHCI_QUIRK_NO_CARD_NO_RESET
|
|
| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
|
.ops = &sdhci_esdhc_be_ops,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
|
|
.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
|
| SDHCI_QUIRK_NO_CARD_NO_RESET
|
|
| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
|
.ops = &sdhci_esdhc_le_ops,
|
|
};
|
|
|
|
static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_esdhc *esdhc;
|
|
u16 host_ver;
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
esdhc = sdhci_pltfm_priv(pltfm_host);
|
|
|
|
host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
|
|
esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
|
|
SDHCI_VENDOR_VER_SHIFT;
|
|
esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
|
|
}
|
|
|
|
static int sdhci_esdhc_probe(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host;
|
|
struct device_node *np;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_esdhc *esdhc;
|
|
int ret;
|
|
|
|
np = pdev->dev.of_node;
|
|
|
|
if (of_property_read_bool(np, "little-endian"))
|
|
host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
|
|
sizeof(struct sdhci_esdhc));
|
|
else
|
|
host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
|
|
sizeof(struct sdhci_esdhc));
|
|
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
esdhc_init(pdev, host);
|
|
|
|
sdhci_get_of_property(pdev);
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
esdhc = sdhci_pltfm_priv(pltfm_host);
|
|
if (esdhc->vendor_ver == VENDOR_V_22)
|
|
host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
|
|
|
|
if (esdhc->vendor_ver > VENDOR_V_22)
|
|
host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
|
|
|
|
if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
|
|
of_device_is_compatible(np, "fsl,p5020-esdhc") ||
|
|
of_device_is_compatible(np, "fsl,p4080-esdhc") ||
|
|
of_device_is_compatible(np, "fsl,p1020-esdhc") ||
|
|
of_device_is_compatible(np, "fsl,t1040-esdhc") ||
|
|
of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
|
|
host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
|
|
|
if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
|
|
|
|
if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
|
|
/*
|
|
* Freescale messed up with P2020 as it has a non-standard
|
|
* host control register
|
|
*/
|
|
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
|
|
}
|
|
|
|
/* call to generic mmc_of_parse to support additional capabilities */
|
|
ret = mmc_of_parse(host->mmc);
|
|
if (ret)
|
|
goto err;
|
|
|
|
mmc_of_parse_voltage(np, &host->ocr_mask);
|
|
|
|
ret = sdhci_add_host(host);
|
|
if (ret)
|
|
goto err;
|
|
|
|
return 0;
|
|
err:
|
|
sdhci_pltfm_free(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id sdhci_esdhc_of_match[] = {
|
|
{ .compatible = "fsl,mpc8379-esdhc" },
|
|
{ .compatible = "fsl,mpc8536-esdhc" },
|
|
{ .compatible = "fsl,esdhc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
|
|
|
|
static struct platform_driver sdhci_esdhc_driver = {
|
|
.driver = {
|
|
.name = "sdhci-esdhc",
|
|
.of_match_table = sdhci_esdhc_of_match,
|
|
.pm = &esdhc_of_dev_pm_ops,
|
|
},
|
|
.probe = sdhci_esdhc_probe,
|
|
.remove = sdhci_pltfm_unregister,
|
|
};
|
|
|
|
module_platform_driver(sdhci_esdhc_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
|
|
MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
|
|
"Anton Vorontsov <avorontsov@ru.mvista.com>");
|
|
MODULE_LICENSE("GPL v2");
|