0fe35077a9
If the system has been started in non-secure mode, then the ARM generic timer is not configurable during the kernel initialisation. Currently the only thing we can check for is if the timer has been correctly configured during the boot process. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Ian Molton <ian.molton@codethink.co.uk> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/*
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* R-Car Generation 2 support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/clocksource.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <mach/common.h>
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#include <mach/rcar-gen2.h>
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#include <asm/mach/arch.h>
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#define MODEMR 0xe6160060
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u32 __init rcar_gen2_read_mode_pins(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, 4);
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u32 mode;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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return mode;
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}
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#define CNTCR 0
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#define CNTFID0 0x20
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void __init rcar_gen2_timer_init(void)
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{
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#ifdef CONFIG_ARM_ARCH_TIMER
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u32 mode = rcar_gen2_read_mode_pins();
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void __iomem *base;
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int extal_mhz = 0;
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u32 freq;
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/* At Linux boot time the r8a7790 arch timer comes up
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* with the counter disabled. Moreover, it may also report
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* a potentially incorrect fixed 13 MHz frequency. To be
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* correct these registers need to be updated to use the
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* frequency EXTAL / 2 which can be determined by the MD pins.
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*/
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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extal_mhz = 15;
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break;
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case MD(13):
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extal_mhz = 20;
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break;
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case MD(14):
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extal_mhz = 26;
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break;
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case MD(13) | MD(14):
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extal_mhz = 30;
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break;
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}
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/* The arch timer frequency equals EXTAL / 2 */
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freq = extal_mhz * (1000000 / 2);
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/* Remap "armgcnt address map" space */
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base = ioremap(0xe6080000, PAGE_SIZE);
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/*
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* Update the timer if it is either not running, or is not at the
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* right frequency. The timer is only configurable in secure mode
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* so this avoids an abort if the loader started the timer and
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* entered the kernel in non-secure mode.
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*/
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if ((ioread32(base + CNTCR) & 1) == 0 ||
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ioread32(base + CNTFID0) != freq) {
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/* Update registers with correct frequency */
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iowrite32(freq, base + CNTFID0);
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
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/* make sure arch timer is started by setting bit 0 of CNTCR */
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iowrite32(1, base + CNTCR);
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}
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iounmap(base);
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#endif /* CONFIG_ARM_ARCH_TIMER */
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clocksource_of_init();
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}
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