![Chris Zankel](/assets/img/avatar_default.png)
Remove io_remap_page_range() from all of Linux 2.6.x (as requested and suggested by Randy Dunlap) and minor clean-ups. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
552 lines
14 KiB
C
552 lines
14 KiB
C
/*
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* arch/xtensa/mm/init.c
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*
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* Derived from MIPS, PPC.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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* Marc Gauthier
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* Kevin Chea
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/bootmem.h>
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#include <linux/swap.h>
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#include <asm/pgtable.h>
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#include <asm/bootparam.h>
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#include <asm/mmu_context.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#define DEBUG 0
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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//static DEFINE_SPINLOCK(tlb_lock);
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/*
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* This flag is used to indicate that the page was mapped and modified in
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* kernel space, so the cache is probably dirty at that address.
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* If cache aliasing is enabled and the page color mismatches, update_mmu_cache
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* synchronizes the caches if this bit is set.
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*/
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#define PG_cache_clean PG_arch_1
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/* References to section boundaries */
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extern char _ftext, _etext, _fdata, _edata, _rodata_end;
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extern char __init_begin, __init_end;
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/*
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* mem_reserve(start, end, must_exist)
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*
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* Reserve some memory from the memory pool.
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*
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* Parameters:
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* start Start of region,
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* end End of region,
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* must_exist Must exist in memory pool.
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*
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* Returns:
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* 0 (memory area couldn't be mapped)
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* -1 (success)
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*/
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int __init mem_reserve(unsigned long start, unsigned long end, int must_exist)
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{
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int i;
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if (start == end)
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return 0;
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start = start & PAGE_MASK;
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end = PAGE_ALIGN(end);
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for (i = 0; i < sysmem.nr_banks; i++)
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if (start < sysmem.bank[i].end
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&& end >= sysmem.bank[i].start)
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break;
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if (i == sysmem.nr_banks) {
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if (must_exist)
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printk (KERN_WARNING "mem_reserve: [0x%0lx, 0x%0lx) "
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"not in any region!\n", start, end);
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return 0;
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}
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if (start > sysmem.bank[i].start) {
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if (end < sysmem.bank[i].end) {
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/* split entry */
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if (sysmem.nr_banks >= SYSMEM_BANKS_MAX)
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panic("meminfo overflow\n");
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sysmem.bank[sysmem.nr_banks].start = end;
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sysmem.bank[sysmem.nr_banks].end = sysmem.bank[i].end;
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sysmem.nr_banks++;
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}
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sysmem.bank[i].end = start;
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} else {
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if (end < sysmem.bank[i].end)
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sysmem.bank[i].start = end;
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else {
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/* remove entry */
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sysmem.nr_banks--;
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sysmem.bank[i].start = sysmem.bank[sysmem.nr_banks].start;
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sysmem.bank[i].end = sysmem.bank[sysmem.nr_banks].end;
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}
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}
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return -1;
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}
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/*
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* Initialize the bootmem system and give it all the memory we have available.
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*/
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void __init bootmem_init(void)
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{
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unsigned long pfn;
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unsigned long bootmap_start, bootmap_size;
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int i;
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max_low_pfn = max_pfn = 0;
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min_low_pfn = ~0;
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for (i=0; i < sysmem.nr_banks; i++) {
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pfn = PAGE_ALIGN(sysmem.bank[i].start) >> PAGE_SHIFT;
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if (pfn < min_low_pfn)
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min_low_pfn = pfn;
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pfn = PAGE_ALIGN(sysmem.bank[i].end - 1) >> PAGE_SHIFT;
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if (pfn > max_pfn)
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max_pfn = pfn;
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}
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if (min_low_pfn > max_pfn)
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panic("No memory found!\n");
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max_low_pfn = max_pfn < MAX_LOW_MEMORY >> PAGE_SHIFT ?
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max_pfn : MAX_LOW_MEMORY >> PAGE_SHIFT;
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/* Find an area to use for the bootmem bitmap. */
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bootmap_size = bootmem_bootmap_pages(max_low_pfn) << PAGE_SHIFT;
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bootmap_start = ~0;
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for (i=0; i<sysmem.nr_banks; i++)
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if (sysmem.bank[i].end - sysmem.bank[i].start >= bootmap_size) {
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bootmap_start = sysmem.bank[i].start;
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break;
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}
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if (bootmap_start == ~0UL)
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panic("Cannot find %ld bytes for bootmap\n", bootmap_size);
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/* Reserve the bootmem bitmap area */
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mem_reserve(bootmap_start, bootmap_start + bootmap_size, 1);
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bootmap_size = init_bootmem_node(NODE_DATA(0), min_low_pfn,
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bootmap_start >> PAGE_SHIFT,
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max_low_pfn);
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/* Add all remaining memory pieces into the bootmem map */
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for (i=0; i<sysmem.nr_banks; i++)
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free_bootmem(sysmem.bank[i].start,
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sysmem.bank[i].end - sysmem.bank[i].start);
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}
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void __init paging_init(void)
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{
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unsigned long zones_size[MAX_NR_ZONES];
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int i;
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/* All pages are DMA-able, so we put them all in the DMA zone. */
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zones_size[ZONE_DMA] = max_low_pfn;
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for (i = 1; i < MAX_NR_ZONES; i++)
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zones_size[i] = 0;
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#ifdef CONFIG_HIGHMEM
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zones_size[ZONE_HIGHMEM] = max_pfn - max_low_pfn;
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#endif
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/* Initialize the kernel's page tables. */
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memset(swapper_pg_dir, 0, PAGE_SIZE);
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free_area_init(zones_size);
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}
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/*
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* Flush the mmu and reset associated register to default values.
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*/
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void __init init_mmu (void)
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{
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/* Writing zeros to the <t>TLBCFG special registers ensure
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* that valid values exist in the register. For existing
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* PGSZID<w> fields, zero selects the first element of the
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* page-size array. For nonexistant PGSZID<w> fields, zero is
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* the best value to write. Also, when changing PGSZID<w>
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* fields, the corresponding TLB must be flushed.
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*/
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set_itlbcfg_register (0);
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set_dtlbcfg_register (0);
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flush_tlb_all ();
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/* Set rasid register to a known value. */
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set_rasid_register (ASID_ALL_RESERVED);
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/* Set PTEVADDR special register to the start of the page
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* table, which is in kernel mappable space (ie. not
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* statically mapped). This register's value is undefined on
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* reset.
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*/
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set_ptevaddr_register (PGTABLE_START);
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}
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/*
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* Initialize memory pages.
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*/
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void __init mem_init(void)
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{
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unsigned long codesize, reservedpages, datasize, initsize;
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unsigned long highmemsize, tmp, ram;
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max_mapnr = num_physpages = max_low_pfn;
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high_memory = (void *) __va(max_mapnr << PAGE_SHIFT);
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highmemsize = 0;
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#ifdef CONFIG_HIGHMEM
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#error HIGHGMEM not implemented in init.c
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#endif
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totalram_pages += free_all_bootmem();
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reservedpages = ram = 0;
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for (tmp = 0; tmp < max_low_pfn; tmp++) {
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ram++;
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if (PageReserved(mem_map+tmp))
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reservedpages++;
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}
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codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
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datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
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initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
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printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, "
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"%ldk data, %ldk init %ldk highmem)\n",
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(unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
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ram << (PAGE_SHIFT-10),
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codesize >> 10,
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reservedpages << (PAGE_SHIFT-10),
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datasize >> 10,
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initsize >> 10,
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highmemsize >> 10);
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}
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void
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free_reserved_mem(void *start, void *end)
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{
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for (; start < end; start += PAGE_SIZE) {
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ClearPageReserved(virt_to_page(start));
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set_page_count(virt_to_page(start), 1);
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free_page((unsigned long)start);
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totalram_pages++;
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}
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}
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#ifdef CONFIG_BLK_DEV_INITRD
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extern int initrd_is_mapped;
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void free_initrd_mem(unsigned long start, unsigned long end)
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{
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if (initrd_is_mapped) {
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free_reserved_mem((void*)start, (void*)end);
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printk ("Freeing initrd memory: %ldk freed\n",(end-start)>>10);
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}
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}
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#endif
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void free_initmem(void)
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{
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free_reserved_mem(&__init_begin, &__init_end);
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printk("Freeing unused kernel memory: %dk freed\n",
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(&__init_end - &__init_begin) >> 10);
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}
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void show_mem(void)
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{
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int i, free = 0, total = 0, reserved = 0;
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int shared = 0, cached = 0;
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printk("Mem-info:\n");
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show_free_areas();
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printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
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i = max_mapnr;
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while (i-- > 0) {
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total++;
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if (PageReserved(mem_map+i))
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reserved++;
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else if (PageSwapCache(mem_map+i))
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cached++;
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else if (!page_count(mem_map + i))
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free++;
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else
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shared += page_count(mem_map + i) - 1;
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}
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printk("%d pages of RAM\n", total);
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printk("%d reserved pages\n", reserved);
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printk("%d pages shared\n", shared);
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printk("%d pages swap cached\n",cached);
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printk("%d free pages\n", free);
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}
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/* ------------------------------------------------------------------------- */
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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/*
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* With cache aliasing, the page color of the page in kernel space and user
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* space might mismatch. We temporarily map the page to a different virtual
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* address with the same color and clear the page there.
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*/
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void clear_user_page(void *kaddr, unsigned long vaddr, struct page* page)
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{
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/* There shouldn't be any entries for this page. */
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__flush_invalidate_dcache_page_phys(__pa(page_address(page)));
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if (!PAGE_COLOR_EQ(vaddr, kaddr)) {
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unsigned long v, p;
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/* Temporarily map page to DTLB_WAY_DCACHE_ALIAS0. */
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spin_lock(&tlb_lock);
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p = (unsigned long)pte_val((mk_pte(page,PAGE_KERNEL)));
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kaddr = (void*)PAGE_COLOR_MAP0(vaddr);
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v = (unsigned long)kaddr | DTLB_WAY_DCACHE_ALIAS0;
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__asm__ __volatile__("wdtlb %0,%1; dsync" : :"a" (p), "a" (v));
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clear_page(kaddr);
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spin_unlock(&tlb_lock);
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} else {
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clear_page(kaddr);
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}
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/* We need to make sure that i$ and d$ are coherent. */
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clear_bit(PG_cache_clean, &page->flags);
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}
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/*
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* With cache aliasing, we have to make sure that the page color of the page
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* in kernel space matches that of the virtual user address before we read
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* the page. If the page color differ, we create a temporary DTLB entry with
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* the corrent page color and use this 'temporary' address as the source.
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* We then use the same approach as in clear_user_page and copy the data
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* to the kernel space and clear the PG_cache_clean bit to synchronize caches
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* later.
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*
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* Note:
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* Instead of using another 'way' for the temporary DTLB entry, we could
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* probably use the same entry that points to the kernel address (after
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* saving the original value and restoring it when we are done).
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*/
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void copy_user_page(void* to, void* from, unsigned long vaddr,
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struct page* to_page)
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{
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/* There shouldn't be any entries for the new page. */
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__flush_invalidate_dcache_page_phys(__pa(page_address(to_page)));
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spin_lock(&tlb_lock);
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if (!PAGE_COLOR_EQ(vaddr, from)) {
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unsigned long v, p, t;
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__asm__ __volatile__ ("pdtlb %1,%2; rdtlb1 %0,%1"
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: "=a"(p), "=a"(t) : "a"(from));
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from = (void*)PAGE_COLOR_MAP0(vaddr);
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v = (unsigned long)from | DTLB_WAY_DCACHE_ALIAS0;
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__asm__ __volatile__ ("wdtlb %0,%1; dsync" ::"a" (p), "a" (v));
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}
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if (!PAGE_COLOR_EQ(vaddr, to)) {
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unsigned long v, p;
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p = (unsigned long)pte_val((mk_pte(to_page,PAGE_KERNEL)));
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to = (void*)PAGE_COLOR_MAP1(vaddr);
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v = (unsigned long)to | DTLB_WAY_DCACHE_ALIAS1;
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__asm__ __volatile__ ("wdtlb %0,%1; dsync" ::"a" (p), "a" (v));
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}
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copy_page(to, from);
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spin_unlock(&tlb_lock);
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/* We need to make sure that i$ and d$ are coherent. */
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clear_bit(PG_cache_clean, &to_page->flags);
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}
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/*
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* Any time the kernel writes to a user page cache page, or it is about to
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* read from a page cache page this routine is called.
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*
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* Note:
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* The kernel currently only provides one architecture bit in the page
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* flags that we use for I$/D$ coherency. Maybe, in future, we can
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* use a sepearte bit for deferred dcache aliasing:
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* If the page is not mapped yet, we only need to set a flag,
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* if mapped, we need to invalidate the page.
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*/
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// FIXME: we probably need this for WB caches not only for Page Coloring..
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void flush_dcache_page(struct page *page)
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{
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unsigned long addr = __pa(page_address(page));
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struct address_space *mapping = page_mapping(page);
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__flush_invalidate_dcache_page_phys(addr);
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if (!test_bit(PG_cache_clean, &page->flags))
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return;
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/* If this page hasn't been mapped, yet, handle I$/D$ coherency later.*/
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#if 0
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if (mapping && !mapping_mapped(mapping))
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clear_bit(PG_cache_clean, &page->flags);
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else
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#endif
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__invalidate_icache_page_phys(addr);
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}
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void flush_cache_range(struct vm_area_struct* vma, unsigned long s,
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unsigned long e)
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{
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__flush_invalidate_cache_all();
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}
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void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
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unsigned long pfn)
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{
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struct page *page = pfn_to_page(pfn);
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/* Remove any entry for the old mapping. */
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if (current->active_mm == vma->vm_mm) {
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unsigned long addr = __pa(page_address(page));
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__flush_invalidate_dcache_page_phys(addr);
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if ((vma->vm_flags & VM_EXEC) != 0)
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__invalidate_icache_page_phys(addr);
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} else {
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BUG();
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}
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}
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#endif /* (DCACHE_WAY_SIZE > PAGE_SIZE) */
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pte_t* pte_alloc_one_kernel (struct mm_struct* mm, unsigned long addr)
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{
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pte_t* pte = (pte_t*)__get_free_pages(GFP_KERNEL|__GFP_REPEAT, 0);
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if (likely(pte)) {
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pte_t* ptep = (pte_t*)(pte_val(*pte) + PAGE_OFFSET);
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int i;
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for (i = 0; i < 1024; i++, ptep++)
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pte_clear(mm, addr, ptep);
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}
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return pte;
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}
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struct page* pte_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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struct page *page;
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page = alloc_pages(GFP_KERNEL | __GFP_REPEAT, 0);
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if (likely(page)) {
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pte_t* ptep = kmap_atomic(page, KM_USER0);
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int i;
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for (i = 0; i < 1024; i++, ptep++)
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pte_clear(mm, addr, ptep);
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kunmap_atomic(ptep, KM_USER0);
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}
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return page;
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}
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/*
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* Handle D$/I$ coherency.
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*
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* Note:
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* We only have one architecture bit for the page flags, so we cannot handle
|
|
* cache aliasing, yet.
|
|
*/
|
|
|
|
void
|
|
update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte)
|
|
{
|
|
unsigned long pfn = pte_pfn(pte);
|
|
struct page *page;
|
|
unsigned long vaddr = addr & PAGE_MASK;
|
|
|
|
if (!pfn_valid(pfn))
|
|
return;
|
|
|
|
page = pfn_to_page(pfn);
|
|
|
|
invalidate_itlb_mapping(addr);
|
|
invalidate_dtlb_mapping(addr);
|
|
|
|
/* We have a new mapping. Use it. */
|
|
|
|
write_dtlb_entry(pte, dtlb_probe(addr));
|
|
|
|
/* If the processor can execute from this page, synchronize D$/I$. */
|
|
|
|
if ((vma->vm_flags & VM_EXEC) != 0) {
|
|
|
|
write_itlb_entry(pte, itlb_probe(addr));
|
|
|
|
/* Synchronize caches, if not clean. */
|
|
|
|
if (!test_and_set_bit(PG_cache_clean, &page->flags)) {
|
|
__flush_dcache_page(vaddr);
|
|
__invalidate_icache_page(vaddr);
|
|
}
|
|
}
|
|
}
|
|
|