367b8112fe
Move all header files for xtensa to arch/xtensa/include and platform and variant header files to the appropriate arch/xtensa/platforms/ and arch/xtensa/variants/ directories. Moving the files gets also rid of all uses of symlinks in the Makefile. This has been completed already for the majority of the architectures and xtensa is one out of six missing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Chris Zankel <chris@zankel.net>
410 lines
8.9 KiB
ArmAsm
410 lines
8.9 KiB
ArmAsm
/*
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* INET An implementation of the TCP/IP protocol suite for the LINUX
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* operating system. INET is implemented using the BSD Socket
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* interface as the means of communication with the user level.
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*
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* IP/TCP/UDP checksumming routines
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*
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* Xtensa version: Copyright (C) 2001 Tensilica, Inc. by Kevin Chea
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* Optimized by Joe Taylor
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/errno.h>
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#include <linux/linkage.h>
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#include <variant/core.h>
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/*
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* computes a partial checksum, e.g. for TCP/UDP fragments
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*/
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/*
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* unsigned int csum_partial(const unsigned char *buf, int len,
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* unsigned int sum);
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* a2 = buf
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* a3 = len
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* a4 = sum
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*
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* This function assumes 2- or 4-byte alignment. Other alignments will fail!
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*/
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/* ONES_ADD converts twos-complement math to ones-complement. */
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#define ONES_ADD(sum, val) \
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add sum, sum, val ; \
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bgeu sum, val, 99f ; \
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addi sum, sum, 1 ; \
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99: ;
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.text
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ENTRY(csum_partial)
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/*
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* Experiments with Ethernet and SLIP connections show that buf
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* is aligned on either a 2-byte or 4-byte boundary.
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*/
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entry sp, 32
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extui a5, a2, 0, 2
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bnez a5, 8f /* branch if 2-byte aligned */
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/* Fall-through on common case, 4-byte alignment */
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1:
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srli a5, a3, 5 /* 32-byte chunks */
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#if XCHAL_HAVE_LOOPS
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loopgtz a5, 2f
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#else
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beqz a5, 2f
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slli a5, a5, 5
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add a5, a5, a2 /* a5 = end of last 32-byte chunk */
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.Loop1:
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#endif
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l32i a6, a2, 0
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l32i a7, a2, 4
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ONES_ADD(a4, a6)
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ONES_ADD(a4, a7)
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l32i a6, a2, 8
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l32i a7, a2, 12
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ONES_ADD(a4, a6)
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ONES_ADD(a4, a7)
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l32i a6, a2, 16
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l32i a7, a2, 20
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ONES_ADD(a4, a6)
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ONES_ADD(a4, a7)
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l32i a6, a2, 24
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l32i a7, a2, 28
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ONES_ADD(a4, a6)
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ONES_ADD(a4, a7)
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addi a2, a2, 4*8
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#if !XCHAL_HAVE_LOOPS
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blt a2, a5, .Loop1
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#endif
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2:
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extui a5, a3, 2, 3 /* remaining 4-byte chunks */
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#if XCHAL_HAVE_LOOPS
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loopgtz a5, 3f
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#else
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beqz a5, 3f
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slli a5, a5, 2
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add a5, a5, a2 /* a5 = end of last 4-byte chunk */
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.Loop2:
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#endif
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l32i a6, a2, 0
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ONES_ADD(a4, a6)
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addi a2, a2, 4
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#if !XCHAL_HAVE_LOOPS
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blt a2, a5, .Loop2
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#endif
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3:
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_bbci.l a3, 1, 5f /* remaining 2-byte chunk */
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l16ui a6, a2, 0
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ONES_ADD(a4, a6)
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addi a2, a2, 2
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5:
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_bbci.l a3, 0, 7f /* remaining 1-byte chunk */
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6: l8ui a6, a2, 0
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#ifdef __XTENSA_EB__
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slli a6, a6, 8 /* load byte into bits 8..15 */
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#endif
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ONES_ADD(a4, a6)
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7:
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mov a2, a4
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retw
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/* uncommon case, buf is 2-byte aligned */
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8:
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beqz a3, 7b /* branch if len == 0 */
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beqi a3, 1, 6b /* branch if len == 1 */
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extui a5, a2, 0, 1
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bnez a5, 8f /* branch if 1-byte aligned */
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l16ui a6, a2, 0 /* common case, len >= 2 */
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ONES_ADD(a4, a6)
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addi a2, a2, 2 /* adjust buf */
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addi a3, a3, -2 /* adjust len */
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j 1b /* now buf is 4-byte aligned */
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/* case: odd-byte aligned, len > 1
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* This case is dog slow, so don't give us an odd address.
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* (I don't think this ever happens, but just in case.)
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*/
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8:
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srli a5, a3, 2 /* 4-byte chunks */
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#if XCHAL_HAVE_LOOPS
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loopgtz a5, 2f
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#else
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beqz a5, 2f
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slli a5, a5, 2
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add a5, a5, a2 /* a5 = end of last 4-byte chunk */
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.Loop3:
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#endif
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l8ui a6, a2, 0 /* bits 24..31 */
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l16ui a7, a2, 1 /* bits 8..23 */
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l8ui a8, a2, 3 /* bits 0.. 8 */
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#ifdef __XTENSA_EB__
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slli a6, a6, 24
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#else
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slli a8, a8, 24
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#endif
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slli a7, a7, 8
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or a7, a7, a6
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or a7, a7, a8
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ONES_ADD(a4, a7)
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addi a2, a2, 4
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#if !XCHAL_HAVE_LOOPS
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blt a2, a5, .Loop3
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#endif
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2:
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_bbci.l a3, 1, 3f /* remaining 2-byte chunk, still odd addr */
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l8ui a6, a2, 0
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l8ui a7, a2, 1
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#ifdef __XTENSA_EB__
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slli a6, a6, 8
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#else
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slli a7, a7, 8
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#endif
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or a7, a7, a6
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ONES_ADD(a4, a7)
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addi a2, a2, 2
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3:
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j 5b /* branch to handle the remaining byte */
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/*
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* Copy from ds while checksumming, otherwise like csum_partial
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*
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* The macros SRC and DST specify the type of access for the instruction.
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* thus we can call a custom exception handler for each access type.
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*/
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#define SRC(y...) \
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9999: y; \
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.section __ex_table, "a"; \
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.long 9999b, 6001f ; \
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.previous
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#define DST(y...) \
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9999: y; \
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.section __ex_table, "a"; \
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.long 9999b, 6002f ; \
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.previous
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/*
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unsigned int csum_partial_copy_generic (const char *src, char *dst, int len,
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int sum, int *src_err_ptr, int *dst_err_ptr)
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a2 = src
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a3 = dst
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a4 = len
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a5 = sum
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a6 = src_err_ptr
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a7 = dst_err_ptr
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a8 = temp
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a9 = temp
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a10 = temp
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a11 = original len for exception handling
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a12 = original dst for exception handling
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This function is optimized for 4-byte aligned addresses. Other
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alignments work, but not nearly as efficiently.
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*/
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ENTRY(csum_partial_copy_generic)
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entry sp, 32
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mov a12, a3
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mov a11, a4
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or a10, a2, a3
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/* We optimize the following alignment tests for the 4-byte
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aligned case. Two bbsi.l instructions might seem more optimal
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(commented out below). However, both labels 5: and 3: are out
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of the imm8 range, so the assembler relaxes them into
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equivalent bbci.l, j combinations, which is actually
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slower. */
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extui a9, a10, 0, 2
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beqz a9, 1f /* branch if both are 4-byte aligned */
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bbsi.l a10, 0, 5f /* branch if one address is odd */
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j 3f /* one address is 2-byte aligned */
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/* _bbsi.l a10, 0, 5f */ /* branch if odd address */
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/* _bbsi.l a10, 1, 3f */ /* branch if 2-byte-aligned address */
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1:
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/* src and dst are both 4-byte aligned */
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srli a10, a4, 5 /* 32-byte chunks */
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#if XCHAL_HAVE_LOOPS
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loopgtz a10, 2f
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#else
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beqz a10, 2f
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slli a10, a10, 5
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add a10, a10, a2 /* a10 = end of last 32-byte src chunk */
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.Loop5:
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#endif
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SRC( l32i a9, a2, 0 )
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SRC( l32i a8, a2, 4 )
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DST( s32i a9, a3, 0 )
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DST( s32i a8, a3, 4 )
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ONES_ADD(a5, a9)
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ONES_ADD(a5, a8)
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SRC( l32i a9, a2, 8 )
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SRC( l32i a8, a2, 12 )
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DST( s32i a9, a3, 8 )
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DST( s32i a8, a3, 12 )
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ONES_ADD(a5, a9)
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ONES_ADD(a5, a8)
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SRC( l32i a9, a2, 16 )
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SRC( l32i a8, a2, 20 )
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DST( s32i a9, a3, 16 )
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DST( s32i a8, a3, 20 )
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ONES_ADD(a5, a9)
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ONES_ADD(a5, a8)
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SRC( l32i a9, a2, 24 )
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SRC( l32i a8, a2, 28 )
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DST( s32i a9, a3, 24 )
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DST( s32i a8, a3, 28 )
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ONES_ADD(a5, a9)
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ONES_ADD(a5, a8)
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addi a2, a2, 32
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addi a3, a3, 32
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#if !XCHAL_HAVE_LOOPS
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blt a2, a10, .Loop5
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#endif
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2:
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extui a10, a4, 2, 3 /* remaining 4-byte chunks */
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extui a4, a4, 0, 2 /* reset len for general-case, 2-byte chunks */
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#if XCHAL_HAVE_LOOPS
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loopgtz a10, 3f
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#else
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beqz a10, 3f
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slli a10, a10, 2
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add a10, a10, a2 /* a10 = end of last 4-byte src chunk */
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.Loop6:
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#endif
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SRC( l32i a9, a2, 0 )
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DST( s32i a9, a3, 0 )
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ONES_ADD(a5, a9)
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addi a2, a2, 4
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addi a3, a3, 4
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#if !XCHAL_HAVE_LOOPS
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blt a2, a10, .Loop6
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#endif
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3:
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/*
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Control comes to here in two cases: (1) It may fall through
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to here from the 4-byte alignment case to process, at most,
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one 2-byte chunk. (2) It branches to here from above if
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either src or dst is 2-byte aligned, and we process all bytes
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here, except for perhaps a trailing odd byte. It's
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inefficient, so align your addresses to 4-byte boundaries.
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a2 = src
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a3 = dst
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a4 = len
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a5 = sum
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*/
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srli a10, a4, 1 /* 2-byte chunks */
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#if XCHAL_HAVE_LOOPS
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loopgtz a10, 4f
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#else
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beqz a10, 4f
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slli a10, a10, 1
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add a10, a10, a2 /* a10 = end of last 2-byte src chunk */
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.Loop7:
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#endif
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SRC( l16ui a9, a2, 0 )
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DST( s16i a9, a3, 0 )
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ONES_ADD(a5, a9)
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addi a2, a2, 2
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addi a3, a3, 2
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#if !XCHAL_HAVE_LOOPS
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blt a2, a10, .Loop7
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#endif
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4:
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/* This section processes a possible trailing odd byte. */
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_bbci.l a4, 0, 8f /* 1-byte chunk */
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SRC( l8ui a9, a2, 0 )
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DST( s8i a9, a3, 0 )
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#ifdef __XTENSA_EB__
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slli a9, a9, 8 /* shift byte to bits 8..15 */
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#endif
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ONES_ADD(a5, a9)
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8:
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mov a2, a5
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retw
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5:
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/* Control branch to here when either src or dst is odd. We
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process all bytes using 8-bit accesses. Grossly inefficient,
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so don't feed us an odd address. */
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srli a10, a4, 1 /* handle in pairs for 16-bit csum */
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#if XCHAL_HAVE_LOOPS
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loopgtz a10, 6f
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#else
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beqz a10, 6f
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slli a10, a10, 1
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add a10, a10, a2 /* a10 = end of last odd-aligned, 2-byte src chunk */
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.Loop8:
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#endif
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SRC( l8ui a9, a2, 0 )
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SRC( l8ui a8, a2, 1 )
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DST( s8i a9, a3, 0 )
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DST( s8i a8, a3, 1 )
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#ifdef __XTENSA_EB__
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slli a9, a9, 8 /* combine into a single 16-bit value */
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#else /* for checksum computation */
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slli a8, a8, 8
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#endif
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or a9, a9, a8
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ONES_ADD(a5, a9)
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addi a2, a2, 2
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addi a3, a3, 2
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#if !XCHAL_HAVE_LOOPS
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blt a2, a10, .Loop8
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#endif
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6:
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j 4b /* process the possible trailing odd byte */
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# Exception handler:
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.section .fixup, "ax"
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/*
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a6 = src_err_ptr
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a7 = dst_err_ptr
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a11 = original len for exception handling
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a12 = original dst for exception handling
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*/
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6001:
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_movi a2, -EFAULT
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s32i a2, a6, 0 /* src_err_ptr */
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# clear the complete destination - computing the rest
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# is too much work
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movi a2, 0
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#if XCHAL_HAVE_LOOPS
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loopgtz a11, 2f
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#else
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beqz a11, 2f
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add a11, a11, a12 /* a11 = ending address */
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.Leloop:
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#endif
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s8i a2, a12, 0
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addi a12, a12, 1
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#if !XCHAL_HAVE_LOOPS
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blt a12, a11, .Leloop
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#endif
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2:
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retw
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6002:
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movi a2, -EFAULT
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s32i a2, a7, 0 /* dst_err_ptr */
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movi a2, 0
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retw
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.previous
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