7c4e1119a9
The PLL introduces jitter, which in turn introduces noice if used to clock the DAC. Thus, avoid the PLL output, and use the PLL input to drive the DAC clock, if possible. This is described for the PCM5142/PCM5242 chips in the answers to the forum post "PCM5142/PCM5242 DAC clock source" at the TI E2E community pages (1). (1) http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/389994 Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Mark Brown <broonie@kernel.org>
271 lines
10 KiB
C
271 lines
10 KiB
C
/*
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* Driver for the PCM512x CODECs
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*
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* Author: Mark Brown <broonie@linaro.org>
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* Copyright 2014 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef _SND_SOC_PCM512X
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#define _SND_SOC_PCM512X
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#define PCM512x_VIRT_BASE 0x100
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#define PCM512x_PAGE_LEN 0x100
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#define PCM512x_PAGE_BASE(n) (PCM512x_VIRT_BASE + (PCM512x_PAGE_LEN * n))
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#define PCM512x_PAGE 0
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#define PCM512x_RESET (PCM512x_PAGE_BASE(0) + 1)
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#define PCM512x_POWER (PCM512x_PAGE_BASE(0) + 2)
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#define PCM512x_MUTE (PCM512x_PAGE_BASE(0) + 3)
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#define PCM512x_PLL_EN (PCM512x_PAGE_BASE(0) + 4)
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#define PCM512x_SPI_MISO_FUNCTION (PCM512x_PAGE_BASE(0) + 6)
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#define PCM512x_DSP (PCM512x_PAGE_BASE(0) + 7)
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#define PCM512x_GPIO_EN (PCM512x_PAGE_BASE(0) + 8)
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#define PCM512x_BCLK_LRCLK_CFG (PCM512x_PAGE_BASE(0) + 9)
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#define PCM512x_DSP_GPIO_INPUT (PCM512x_PAGE_BASE(0) + 10)
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#define PCM512x_MASTER_MODE (PCM512x_PAGE_BASE(0) + 12)
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#define PCM512x_PLL_REF (PCM512x_PAGE_BASE(0) + 13)
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#define PCM512x_DAC_REF (PCM512x_PAGE_BASE(0) + 14)
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#define PCM512x_GPIO_DACIN (PCM512x_PAGE_BASE(0) + 16)
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#define PCM512x_GPIO_PLLIN (PCM512x_PAGE_BASE(0) + 18)
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#define PCM512x_SYNCHRONIZE (PCM512x_PAGE_BASE(0) + 19)
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#define PCM512x_PLL_COEFF_0 (PCM512x_PAGE_BASE(0) + 20)
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#define PCM512x_PLL_COEFF_1 (PCM512x_PAGE_BASE(0) + 21)
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#define PCM512x_PLL_COEFF_2 (PCM512x_PAGE_BASE(0) + 22)
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#define PCM512x_PLL_COEFF_3 (PCM512x_PAGE_BASE(0) + 23)
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#define PCM512x_PLL_COEFF_4 (PCM512x_PAGE_BASE(0) + 24)
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#define PCM512x_DSP_CLKDIV (PCM512x_PAGE_BASE(0) + 27)
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#define PCM512x_DAC_CLKDIV (PCM512x_PAGE_BASE(0) + 28)
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#define PCM512x_NCP_CLKDIV (PCM512x_PAGE_BASE(0) + 29)
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#define PCM512x_OSR_CLKDIV (PCM512x_PAGE_BASE(0) + 30)
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#define PCM512x_MASTER_CLKDIV_1 (PCM512x_PAGE_BASE(0) + 32)
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#define PCM512x_MASTER_CLKDIV_2 (PCM512x_PAGE_BASE(0) + 33)
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#define PCM512x_FS_SPEED_MODE (PCM512x_PAGE_BASE(0) + 34)
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#define PCM512x_IDAC_1 (PCM512x_PAGE_BASE(0) + 35)
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#define PCM512x_IDAC_2 (PCM512x_PAGE_BASE(0) + 36)
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#define PCM512x_ERROR_DETECT (PCM512x_PAGE_BASE(0) + 37)
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#define PCM512x_I2S_1 (PCM512x_PAGE_BASE(0) + 40)
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#define PCM512x_I2S_2 (PCM512x_PAGE_BASE(0) + 41)
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#define PCM512x_DAC_ROUTING (PCM512x_PAGE_BASE(0) + 42)
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#define PCM512x_DSP_PROGRAM (PCM512x_PAGE_BASE(0) + 43)
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#define PCM512x_CLKDET (PCM512x_PAGE_BASE(0) + 44)
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#define PCM512x_AUTO_MUTE (PCM512x_PAGE_BASE(0) + 59)
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#define PCM512x_DIGITAL_VOLUME_1 (PCM512x_PAGE_BASE(0) + 60)
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#define PCM512x_DIGITAL_VOLUME_2 (PCM512x_PAGE_BASE(0) + 61)
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#define PCM512x_DIGITAL_VOLUME_3 (PCM512x_PAGE_BASE(0) + 62)
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#define PCM512x_DIGITAL_MUTE_1 (PCM512x_PAGE_BASE(0) + 63)
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#define PCM512x_DIGITAL_MUTE_2 (PCM512x_PAGE_BASE(0) + 64)
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#define PCM512x_DIGITAL_MUTE_3 (PCM512x_PAGE_BASE(0) + 65)
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#define PCM512x_GPIO_OUTPUT_1 (PCM512x_PAGE_BASE(0) + 80)
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#define PCM512x_GPIO_OUTPUT_2 (PCM512x_PAGE_BASE(0) + 81)
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#define PCM512x_GPIO_OUTPUT_3 (PCM512x_PAGE_BASE(0) + 82)
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#define PCM512x_GPIO_OUTPUT_4 (PCM512x_PAGE_BASE(0) + 83)
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#define PCM512x_GPIO_OUTPUT_5 (PCM512x_PAGE_BASE(0) + 84)
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#define PCM512x_GPIO_OUTPUT_6 (PCM512x_PAGE_BASE(0) + 85)
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#define PCM512x_GPIO_CONTROL_1 (PCM512x_PAGE_BASE(0) + 86)
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#define PCM512x_GPIO_CONTROL_2 (PCM512x_PAGE_BASE(0) + 87)
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#define PCM512x_OVERFLOW (PCM512x_PAGE_BASE(0) + 90)
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#define PCM512x_RATE_DET_1 (PCM512x_PAGE_BASE(0) + 91)
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#define PCM512x_RATE_DET_2 (PCM512x_PAGE_BASE(0) + 92)
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#define PCM512x_RATE_DET_3 (PCM512x_PAGE_BASE(0) + 93)
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#define PCM512x_RATE_DET_4 (PCM512x_PAGE_BASE(0) + 94)
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#define PCM512x_CLOCK_STATUS (PCM512x_PAGE_BASE(0) + 95)
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#define PCM512x_ANALOG_MUTE_DET (PCM512x_PAGE_BASE(0) + 108)
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#define PCM512x_GPIN (PCM512x_PAGE_BASE(0) + 119)
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#define PCM512x_DIGITAL_MUTE_DET (PCM512x_PAGE_BASE(0) + 120)
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#define PCM512x_OUTPUT_AMPLITUDE (PCM512x_PAGE_BASE(1) + 1)
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#define PCM512x_ANALOG_GAIN_CTRL (PCM512x_PAGE_BASE(1) + 2)
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#define PCM512x_UNDERVOLTAGE_PROT (PCM512x_PAGE_BASE(1) + 5)
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#define PCM512x_ANALOG_MUTE_CTRL (PCM512x_PAGE_BASE(1) + 6)
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#define PCM512x_ANALOG_GAIN_BOOST (PCM512x_PAGE_BASE(1) + 7)
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#define PCM512x_VCOM_CTRL_1 (PCM512x_PAGE_BASE(1) + 8)
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#define PCM512x_VCOM_CTRL_2 (PCM512x_PAGE_BASE(1) + 9)
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#define PCM512x_CRAM_CTRL (PCM512x_PAGE_BASE(44) + 1)
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#define PCM512x_FLEX_A (PCM512x_PAGE_BASE(253) + 63)
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#define PCM512x_FLEX_B (PCM512x_PAGE_BASE(253) + 64)
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#define PCM512x_MAX_REGISTER (PCM512x_PAGE_BASE(253) + 64)
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/* Page 0, Register 1 - reset */
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#define PCM512x_RSTR (1 << 0)
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#define PCM512x_RSTM (1 << 4)
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/* Page 0, Register 2 - power */
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#define PCM512x_RQPD (1 << 0)
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#define PCM512x_RQPD_SHIFT 0
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#define PCM512x_RQST (1 << 4)
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#define PCM512x_RQST_SHIFT 4
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/* Page 0, Register 3 - mute */
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#define PCM512x_RQMR_SHIFT 0
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#define PCM512x_RQML_SHIFT 4
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/* Page 0, Register 4 - PLL */
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#define PCM512x_PLLE (1 << 0)
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#define PCM512x_PLLE_SHIFT 0
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#define PCM512x_PLCK (1 << 4)
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#define PCM512x_PLCK_SHIFT 4
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/* Page 0, Register 7 - DSP */
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#define PCM512x_SDSL (1 << 0)
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#define PCM512x_SDSL_SHIFT 0
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#define PCM512x_DEMP (1 << 4)
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#define PCM512x_DEMP_SHIFT 4
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/* Page 0, Register 8 - GPIO output enable */
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#define PCM512x_G1OE (1 << 0)
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#define PCM512x_G2OE (1 << 1)
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#define PCM512x_G3OE (1 << 2)
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#define PCM512x_G4OE (1 << 3)
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#define PCM512x_G5OE (1 << 4)
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#define PCM512x_G6OE (1 << 5)
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/* Page 0, Register 9 - BCK, LRCLK configuration */
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#define PCM512x_LRKO (1 << 0)
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#define PCM512x_LRKO_SHIFT 0
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#define PCM512x_BCKO (1 << 4)
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#define PCM512x_BCKO_SHIFT 4
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#define PCM512x_BCKP (1 << 5)
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#define PCM512x_BCKP_SHIFT 5
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/* Page 0, Register 12 - Master mode BCK, LRCLK reset */
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#define PCM512x_RLRK (1 << 0)
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#define PCM512x_RLRK_SHIFT 0
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#define PCM512x_RBCK (1 << 1)
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#define PCM512x_RBCK_SHIFT 1
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/* Page 0, Register 13 - PLL reference */
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#define PCM512x_SREF (7 << 4)
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#define PCM512x_SREF_SHIFT 4
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#define PCM512x_SREF_SCK (0 << 4)
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#define PCM512x_SREF_BCK (1 << 4)
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#define PCM512x_SREF_GPIO (3 << 4)
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/* Page 0, Register 14 - DAC reference */
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#define PCM512x_SDAC (7 << 4)
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#define PCM512x_SDAC_SHIFT 4
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#define PCM512x_SDAC_MCK (0 << 4)
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#define PCM512x_SDAC_PLL (1 << 4)
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#define PCM512x_SDAC_SCK (3 << 4)
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#define PCM512x_SDAC_BCK (4 << 4)
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#define PCM512x_SDAC_GPIO (5 << 4)
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/* Page 0, Register 16, 18 - GPIO source for DAC, PLL */
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#define PCM512x_GREF (7 << 0)
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#define PCM512x_GREF_SHIFT 0
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#define PCM512x_GREF_GPIO1 (0 << 0)
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#define PCM512x_GREF_GPIO2 (1 << 0)
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#define PCM512x_GREF_GPIO3 (2 << 0)
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#define PCM512x_GREF_GPIO4 (3 << 0)
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#define PCM512x_GREF_GPIO5 (4 << 0)
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#define PCM512x_GREF_GPIO6 (5 << 0)
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/* Page 0, Register 19 - synchronize */
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#define PCM512x_RQSY (1 << 0)
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#define PCM512x_RQSY_RESUME (0 << 0)
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#define PCM512x_RQSY_HALT (1 << 0)
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/* Page 0, Register 34 - fs speed mode */
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#define PCM512x_FSSP (3 << 0)
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#define PCM512x_FSSP_SHIFT 0
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#define PCM512x_FSSP_48KHZ (0 << 0)
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#define PCM512x_FSSP_96KHZ (1 << 0)
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#define PCM512x_FSSP_192KHZ (2 << 0)
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#define PCM512x_FSSP_384KHZ (3 << 0)
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/* Page 0, Register 37 - Error detection */
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#define PCM512x_IPLK (1 << 0)
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#define PCM512x_DCAS (1 << 1)
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#define PCM512x_IDCM (1 << 2)
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#define PCM512x_IDCH (1 << 3)
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#define PCM512x_IDSK (1 << 4)
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#define PCM512x_IDBK (1 << 5)
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#define PCM512x_IDFS (1 << 6)
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/* Page 0, Register 40 - I2S configuration */
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#define PCM512x_ALEN (3 << 0)
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#define PCM512x_ALEN_SHIFT 0
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#define PCM512x_ALEN_16 (0 << 0)
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#define PCM512x_ALEN_20 (1 << 0)
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#define PCM512x_ALEN_24 (2 << 0)
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#define PCM512x_ALEN_32 (3 << 0)
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#define PCM512x_AFMT (3 << 4)
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#define PCM512x_AFMT_SHIFT 4
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#define PCM512x_AFMT_I2S (0 << 4)
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#define PCM512x_AFMT_DSP (1 << 4)
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#define PCM512x_AFMT_RTJ (2 << 4)
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#define PCM512x_AFMT_LTJ (3 << 4)
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/* Page 0, Register 42 - DAC routing */
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#define PCM512x_AUPR_SHIFT 0
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#define PCM512x_AUPL_SHIFT 4
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/* Page 0, Register 59 - auto mute */
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#define PCM512x_ATMR_SHIFT 0
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#define PCM512x_ATML_SHIFT 4
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/* Page 0, Register 63 - ramp rates */
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#define PCM512x_VNDF_SHIFT 6
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#define PCM512x_VNDS_SHIFT 4
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#define PCM512x_VNUF_SHIFT 2
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#define PCM512x_VNUS_SHIFT 0
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/* Page 0, Register 64 - emergency ramp rates */
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#define PCM512x_VEDF_SHIFT 6
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#define PCM512x_VEDS_SHIFT 4
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/* Page 0, Register 65 - Digital mute enables */
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#define PCM512x_ACTL_SHIFT 2
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#define PCM512x_AMLE_SHIFT 1
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#define PCM512x_AMRE_SHIFT 0
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/* Page 0, Register 80-85, GPIO output selection */
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#define PCM512x_GxSL (31 << 0)
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#define PCM512x_GxSL_SHIFT 0
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#define PCM512x_GxSL_OFF (0 << 0)
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#define PCM512x_GxSL_DSP (1 << 0)
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#define PCM512x_GxSL_REG (2 << 0)
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#define PCM512x_GxSL_AMUTB (3 << 0)
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#define PCM512x_GxSL_AMUTL (4 << 0)
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#define PCM512x_GxSL_AMUTR (5 << 0)
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#define PCM512x_GxSL_CLKI (6 << 0)
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#define PCM512x_GxSL_SDOUT (7 << 0)
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#define PCM512x_GxSL_ANMUL (8 << 0)
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#define PCM512x_GxSL_ANMUR (9 << 0)
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#define PCM512x_GxSL_PLLLK (10 << 0)
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#define PCM512x_GxSL_CPCLK (11 << 0)
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#define PCM512x_GxSL_UV0_7 (14 << 0)
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#define PCM512x_GxSL_UV0_3 (15 << 0)
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#define PCM512x_GxSL_PLLCK (16 << 0)
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/* Page 1, Register 2 - analog volume control */
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#define PCM512x_RAGN_SHIFT 0
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#define PCM512x_LAGN_SHIFT 4
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/* Page 1, Register 7 - analog boost control */
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#define PCM512x_AGBR_SHIFT 0
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#define PCM512x_AGBL_SHIFT 4
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extern const struct dev_pm_ops pcm512x_pm_ops;
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extern const struct regmap_config pcm512x_regmap;
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int pcm512x_probe(struct device *dev, struct regmap *regmap);
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void pcm512x_remove(struct device *dev);
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#endif
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