![Rajendra Nayak](/assets/img/avatar_default.png)
This would be useful in subsequent patches when the .set_rate operation would need to identify if the PLL is actually enabled Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Simplify return statement of is_enabled op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
505 lines
12 KiB
C
505 lines
12 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include "clk-alpha-pll.h"
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#include "common.h"
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#define PLL_MODE 0x00
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# define PLL_OUTCTRL BIT(0)
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# define PLL_BYPASSNL BIT(1)
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# define PLL_RESET_N BIT(2)
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# define PLL_OFFLINE_REQ BIT(7)
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# define PLL_LOCK_COUNT_SHIFT 8
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# define PLL_LOCK_COUNT_MASK 0x3f
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# define PLL_BIAS_COUNT_SHIFT 14
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# define PLL_BIAS_COUNT_MASK 0x3f
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# define PLL_VOTE_FSM_ENA BIT(20)
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# define PLL_FSM_ENA BIT(20)
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# define PLL_VOTE_FSM_RESET BIT(21)
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# define PLL_OFFLINE_ACK BIT(28)
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# define PLL_ACTIVE_FLAG BIT(30)
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# define PLL_LOCK_DET BIT(31)
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#define PLL_L_VAL 0x04
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#define PLL_ALPHA_VAL 0x08
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#define PLL_ALPHA_VAL_U 0x0c
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#define PLL_USER_CTL 0x10
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# define PLL_POST_DIV_SHIFT 8
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# define PLL_POST_DIV_MASK 0xf
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# define PLL_ALPHA_EN BIT(24)
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# define PLL_VCO_SHIFT 20
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# define PLL_VCO_MASK 0x3
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#define PLL_USER_CTL_U 0x14
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#define PLL_CONFIG_CTL 0x18
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#define PLL_CONFIG_CTL_U 0x20
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#define PLL_TEST_CTL 0x1c
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#define PLL_TEST_CTL_U 0x20
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#define PLL_STATUS 0x24
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/*
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* Even though 40 bits are present, use only 32 for ease of calculation.
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*/
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#define ALPHA_REG_BITWIDTH 40
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#define ALPHA_BITWIDTH 32
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#define ALPHA_16BIT_MASK 0xffff
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#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
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struct clk_alpha_pll, clkr)
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#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
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struct clk_alpha_pll_postdiv, clkr)
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static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
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const char *action)
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{
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u32 val, off;
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int count;
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int ret;
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const char *name = clk_hw_get_name(&pll->clkr.hw);
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off = pll->offset;
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return ret;
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for (count = 100; count > 0; count--) {
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return ret;
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if (inverse && !(val & mask))
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return 0;
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else if ((val & mask) == mask)
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return 0;
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udelay(1);
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}
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WARN(1, "%s failed to %s!\n", name, action);
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return -ETIMEDOUT;
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}
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#define wait_for_pll_enable_active(pll) \
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wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
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#define wait_for_pll_enable_lock(pll) \
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wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
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#define wait_for_pll_disable(pll) \
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wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
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#define wait_for_pll_offline(pll) \
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wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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u32 val, mask;
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u32 off = pll->offset;
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regmap_write(regmap, off + PLL_L_VAL, config->l);
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regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
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regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
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regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
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val = config->main_output_mask;
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val |= config->aux_output_mask;
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val |= config->aux2_output_mask;
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val |= config->early_output_mask;
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val |= config->pre_div_val;
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val |= config->post_div_val;
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val |= config->vco_val;
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mask = config->main_output_mask;
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mask |= config->aux_output_mask;
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mask |= config->aux2_output_mask;
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mask |= config->early_output_mask;
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mask |= config->pre_div_mask;
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mask |= config->post_div_mask;
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mask |= config->vco_mask;
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regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
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if (pll->flags & SUPPORTS_FSM_MODE)
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qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
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}
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static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
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{
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int ret;
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u32 val, off;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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off = pll->offset;
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return ret;
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val |= PLL_FSM_ENA;
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if (pll->flags & SUPPORTS_OFFLINE_REQ)
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val &= ~PLL_OFFLINE_REQ;
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ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val);
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if (ret)
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return ret;
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/* Make sure enable request goes through before waiting for update */
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mb();
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return wait_for_pll_enable_active(pll);
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}
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static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
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{
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int ret;
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u32 val, off;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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off = pll->offset;
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return;
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if (pll->flags & SUPPORTS_OFFLINE_REQ) {
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ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
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PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
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if (ret)
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return;
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ret = wait_for_pll_offline(pll);
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if (ret)
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return;
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}
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/* Disable hwfsm */
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ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
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PLL_FSM_ENA, 0);
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if (ret)
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return;
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wait_for_pll_disable(pll);
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}
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static int pll_is_enabled(struct clk_hw *hw, u32 mask)
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{
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int ret;
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u32 val, off;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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off = pll->offset;
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return ret;
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return !!(val & mask);
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}
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static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
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{
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return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
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}
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static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
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{
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return pll_is_enabled(hw, PLL_LOCK_DET);
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}
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static int clk_alpha_pll_enable(struct clk_hw *hw)
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{
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int ret;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, mask, off;
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off = pll->offset;
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mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return ret;
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/* If in FSM mode, just vote for it */
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if (val & PLL_VOTE_FSM_ENA) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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return wait_for_pll_enable_active(pll);
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}
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/* Skip if already enabled */
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if ((val & mask) == mask)
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return 0;
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ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
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PLL_BYPASSNL, PLL_BYPASSNL);
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if (ret)
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return ret;
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/*
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* H/W requires a 5us delay between disabling the bypass and
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* de-asserting the reset.
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*/
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mb();
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udelay(5);
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ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
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PLL_RESET_N, PLL_RESET_N);
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if (ret)
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return ret;
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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return ret;
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ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
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PLL_OUTCTRL, PLL_OUTCTRL);
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/* Ensure that the write above goes through before returning. */
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mb();
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return ret;
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}
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static void clk_alpha_pll_disable(struct clk_hw *hw)
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{
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int ret;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, mask, off;
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off = pll->offset;
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ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
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if (ret)
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return;
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/* If in FSM mode, just unvote it */
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if (val & PLL_VOTE_FSM_ENA) {
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clk_disable_regmap(hw);
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return;
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}
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mask = PLL_OUTCTRL;
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regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
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/* Delay of 2 output clock ticks required until output is disabled */
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mb();
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udelay(1);
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mask = PLL_RESET_N | PLL_BYPASSNL;
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regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
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}
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static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
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{
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return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
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}
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static unsigned long
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alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
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{
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u64 remainder;
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u64 quotient;
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quotient = rate;
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remainder = do_div(quotient, prate);
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*l = quotient;
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if (!remainder) {
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*a = 0;
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return rate;
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}
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/* Upper ALPHA_BITWIDTH bits of Alpha */
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quotient = remainder << ALPHA_BITWIDTH;
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remainder = do_div(quotient, prate);
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if (remainder)
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quotient++;
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*a = quotient;
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return alpha_pll_calc_rate(prate, *l, *a);
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}
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static const struct pll_vco *
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alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
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{
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const struct pll_vco *v = pll->vco_table;
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const struct pll_vco *end = v + pll->num_vco;
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for (; v < end; v++)
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if (rate >= v->min_freq && rate <= v->max_freq)
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return v;
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return NULL;
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}
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static unsigned long
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clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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u32 l, low, high, ctl;
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u64 a = 0, prate = parent_rate;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 off = pll->offset;
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regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
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regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
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if (ctl & PLL_ALPHA_EN) {
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regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
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if (pll->flags & SUPPORTS_16BIT_ALPHA) {
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a = low & ALPHA_16BIT_MASK;
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} else {
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regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U,
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&high);
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a = (u64)high << 32 | low;
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a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
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}
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}
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return alpha_pll_calc_rate(prate, l, a);
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}
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static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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const struct pll_vco *vco;
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u32 l, off = pll->offset;
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u64 a;
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rate = alpha_pll_round_rate(rate, prate, &l, &a);
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vco = alpha_pll_find_vco(pll, rate);
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if (!vco) {
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pr_err("alpha pll not in a valid vco range\n");
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return -EINVAL;
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}
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regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
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if (pll->flags & SUPPORTS_16BIT_ALPHA) {
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regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL,
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a & ALPHA_16BIT_MASK);
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} else {
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a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
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regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
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}
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regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
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PLL_VCO_MASK << PLL_VCO_SHIFT,
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vco->val << PLL_VCO_SHIFT);
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regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
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PLL_ALPHA_EN);
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return 0;
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}
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static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 l;
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u64 a;
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unsigned long min_freq, max_freq;
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rate = alpha_pll_round_rate(rate, *prate, &l, &a);
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if (alpha_pll_find_vco(pll, rate))
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return rate;
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min_freq = pll->vco_table[0].min_freq;
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max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
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return clamp(rate, min_freq, max_freq);
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}
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const struct clk_ops clk_alpha_pll_ops = {
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.enable = clk_alpha_pll_enable,
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.disable = clk_alpha_pll_disable,
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.is_enabled = clk_alpha_pll_is_enabled,
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.recalc_rate = clk_alpha_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = clk_alpha_pll_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
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const struct clk_ops clk_alpha_pll_hwfsm_ops = {
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.enable = clk_alpha_pll_hwfsm_enable,
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.disable = clk_alpha_pll_hwfsm_disable,
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.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
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.recalc_rate = clk_alpha_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = clk_alpha_pll_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
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static unsigned long
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clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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u32 ctl;
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regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
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ctl >>= PLL_POST_DIV_SHIFT;
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ctl &= PLL_POST_DIV_MASK;
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return parent_rate >> fls(ctl);
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}
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static const struct clk_div_table clk_alpha_div_table[] = {
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{ 0x0, 1 },
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{ 0x1, 2 },
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{ 0x3, 4 },
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{ 0x7, 8 },
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{ 0xf, 16 },
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{ }
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};
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static long
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clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
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pll->width, CLK_DIVIDER_POWER_OF_TWO);
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}
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static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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int div;
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/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
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return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
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PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
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div << PLL_POST_DIV_SHIFT);
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}
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const struct clk_ops clk_alpha_pll_postdiv_ops = {
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.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
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.round_rate = clk_alpha_pll_postdiv_round_rate,
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.set_rate = clk_alpha_pll_postdiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
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