353 lines
8.3 KiB
C
353 lines
8.3 KiB
C
/*
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* Copyright 2018 NXP
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file vpu_encoder_b0.h
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*
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* @brief VPU ENCODER B0 definition
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*
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*/
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#ifndef __VPU_ENCODER_B0_H__
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#define __VPU_ENCODER_B0_H__
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#include <linux/irqreturn.h>
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#include <linux/mutex.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fh.h>
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#include <media/videobuf2-v4l2.h>
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#include <soc/imx8/sc/svc/irq/api.h>
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#include <soc/imx8/sc/ipc.h>
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#include <soc/imx8/sc/sci.h>
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#include <linux/mx8_mu.h>
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#include <media/v4l2-event.h>
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#include <linux/kfifo.h>
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#include "vpu_encoder_rpc.h"
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extern unsigned int vpu_dbg_level_encoder;
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#define v4l2_fh_to_ctx(__fh) \
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container_of(__fh, struct vpu_ctx, fh)
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#define v4l2_ctrl_to_ctx(__ctrl) \
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container_of((__ctrl)->handler, struct vpu_ctx, ctrl_handler)
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#define MIN_SPACE 2048
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#define VPU_MAX_FORMATS 4
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#define VPU_MAX_BUFFER 32
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#define M0FW_FILENAME "vpu/vpu_fw_imx8_enc.bin"
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#define MMAP_BUF_TYPE_SHIFT 28
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#define MMAP_BUF_TYPE_MASK 0xF0000000
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#define M0_BOOT_SIZE_DEFAULT 0x1000000
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#define M0_BOOT_SIZE_MIN 0x100000
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#define RPC_SIZE_DEFAULT 0x500000
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#define RPC_SIZE_MIN 0x100000
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#define PRINT_SIZE_DEFAULT 0x300000
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#define PRINT_SIZE_MIN 0x100000
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#define MEM_SIZE 0x2800000
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#define YUV_SIZE 0x4000000
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#define STREAM_SIZE 0x300000
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#define VPU_REG_BASE 0x40000000
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#define ENC_REG_BASE 0x2c000000
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#define MIN_BUFFER_COUNT 3
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#define BITRATE_LOW_THRESHOLD 64
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#define BITRATE_HIGH_THRESHOLD 1048576
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#define BITRATE_DEFAULT_TARGET 2048
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#define BITRATE_DEFAULT_PEAK 4096
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#define GOP_H_THRESHOLD 300
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#define GOP_L_THRESHOLD 1
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#define GOP_DEFAULT 30
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#define QP_MAX 51
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#define QP_MIN 0
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#define QP_DEFAULT 25
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#define ENCODER_NODE_NUMBER 13 //use /dev/video13 as encoder node
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struct vpu_v4l2_control {
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uint32_t id;
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enum v4l2_ctrl_type type;
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uint32_t minimum;
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uint32_t maximum;
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uint32_t step;
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uint32_t default_value;
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uint32_t menu_skip_mask;
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bool is_volatile;
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};
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typedef enum{
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INIT_DONE = 1,
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RPC_BUF_OFFSET,
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PRINT_BUF_OFFSET,
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BOOT_ADDRESS,
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COMMAND,
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EVENT
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} MSG_Type;
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enum PLAT_TYPE {
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IMX8QXP = 0,
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IMX8QM = 1,
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};
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enum QUEUE_TYPE {
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V4L2_SRC = 0,
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V4L2_DST = 1,
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};
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enum vpu_video_standard {
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VPU_VIDEO_UNDEFINED = 0,
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VPU_VIDEO_AVC = 1,
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VPU_VIDEO_VC1 = 2,
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VPU_VIDEO_MPEG2 = 3,
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VPU_VIDEO_AVS = 4,
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VPU_VIDEO_ASP = 5,
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VPU_VIDEO_JPEG = 6,
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VPU_VIDEO_RV8 = 7,
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VPU_VIDEO_RV9 = 8,
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VPU_VIDEO_VP6 = 9,
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VPU_VIDEO_SPK = 10,
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VPU_VIDEO_VP8 = 11,
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VPU_VIDEO_AVC_MVC = 12,
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VPU_VIDEO_HEVC = 13,
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VPU_VIDEO_VP9 = 14,
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};
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#define VPU_PIX_FMT_AVS v4l2_fourcc('A', 'V', 'S', '0')
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#define VPU_PIX_FMT_ASP v4l2_fourcc('A', 'S', 'P', '0')
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#define VPU_PIX_FMT_RV8 v4l2_fourcc('R', 'V', '8', '0')
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#define VPU_PIX_FMT_RV9 v4l2_fourcc('R', 'V', '9', '0')
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#define VPU_PIX_FMT_VP6 v4l2_fourcc('V', 'P', '6', '0')
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#define VPU_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0')
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#define VPU_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C')
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#define VPU_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0')
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#define VPU_PIX_FMT_LOGO v4l2_fourcc('L', 'O', 'G', 'O')
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#define VPU_PIX_FMT_TILED_8 v4l2_fourcc('Z', 'T', '0', '8')
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#define VPU_PIX_FMT_TILED_10 v4l2_fourcc('Z', 'T', '1', '0')
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enum vpu_pixel_format {
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VPU_HAS_COLOCATED = 0x00000001,
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VPU_HAS_SPLIT_FLD = 0x00000002,
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VPU_PF_MASK = ~(VPU_HAS_COLOCATED | VPU_HAS_SPLIT_FLD),
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VPU_IS_TILED = 0x000000100,
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VPU_HAS_10BPP = 0x00000200,
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VPU_IS_PLANAR = 0x00001000,
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VPU_IS_SEMIPLANAR = 0x00002000,
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VPU_IS_PACKED = 0x00004000,
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// Merged definitions using above flags:
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VPU_PF_UNDEFINED = 0,
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VPU_PF_YUV420_SEMIPLANAR = 0x00010000 | VPU_IS_SEMIPLANAR,
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VPU_PF_YUV420_PLANAR = 0x00020000 | VPU_IS_PLANAR,
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VPU_PF_UYVY = 0x00040000 | VPU_IS_PACKED,
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VPU_PF_TILED_8BPP = 0x00080000 | VPU_IS_TILED | VPU_IS_SEMIPLANAR,
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VPU_PF_TILED_10BPP = 0x00100000 | VPU_IS_TILED | VPU_IS_SEMIPLANAR | VPU_HAS_10BPP,
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};
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struct vpu_ctx;
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struct core_device;
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struct vpu_dev;
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struct vpu_v4l2_fmt {
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char *name;
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unsigned int fourcc;
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unsigned int num_planes;
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unsigned int venc_std;
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unsigned int is_yuv;
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};
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struct vb2_data_req {
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struct list_head list;
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struct vb2_buffer *vb2_buf;
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int id;
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u_int32 buffer_flags;
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};
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enum ENC_RW_FLAG {
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VPU_ENC_FLAG_WRITEABLE,
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VPU_ENC_FLAG_READABLE
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};
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struct queue_data {
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unsigned int width;
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unsigned int height;
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unsigned int bytesperline;
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unsigned int sizeimage[3];
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unsigned int fourcc;
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unsigned int vdec_std;
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struct v4l2_rect rect;
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int buf_type; // v4l2_buf_type
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bool vb2_q_inited;
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struct vb2_queue vb2_q; // vb2 queue
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struct list_head drv_q; // driver queue
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struct semaphore drv_q_lock;
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struct vb2_data_req vb2_reqs[VPU_MAX_BUFFER];
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enum QUEUE_TYPE type;
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struct vpu_v4l2_fmt *supported_fmts;
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unsigned int fmt_count;
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struct vpu_v4l2_fmt *current_fmt;
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unsigned long rw_flag;
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struct list_head frame_q;
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struct vpu_ctx *ctx;
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};
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struct vpu_statistic {
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unsigned long cmd[GTB_ENC_CMD_RESERVED + 1];
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unsigned long event[VID_API_ENC_EVENT_RESERVED + 1];
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unsigned long current_cmd;
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unsigned long current_event;
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struct timespec ts_cmd;
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struct timespec ts_event;
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unsigned long yuv_count;
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unsigned long encoded_count;
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unsigned long h264_count;
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};
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struct vpu_attr {
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struct device_attribute dev_attr;
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char name[64];
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u32 index;
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struct core_device *core;
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pid_t pid;
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pid_t tgid;
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struct vpu_statistic statistic;
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MEDIAIP_ENC_PARAM param;
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bool created;
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};
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struct core_device {
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void *m0_p_fw_space_vir;
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u_int32 m0_p_fw_space_phy;
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u32 fw_buf_size;
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u32 fw_actual_size;
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void *m0_rpc_virt;
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u_int32 m0_rpc_phy;
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u32 rpc_buf_size;
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u32 print_buf_size;
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u32 rpc_actual_size;
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struct mutex core_mutex;
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struct mutex cmd_mutex;
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bool fw_is_ready;
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bool firmware_started;
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struct completion start_cmp;
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struct completion snap_done_cmp;
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struct workqueue_struct *workqueue;
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struct work_struct msg_work;
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void __iomem *mu_base_virtaddr;
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unsigned int vpu_mu_id;
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int vpu_mu_init;
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struct vpu_ctx *ctx[VPU_MAX_NUM_STREAMS];
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struct vpu_attr attr[VPU_MAX_NUM_STREAMS];
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struct shared_addr shared_mem;
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u32 id;
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off_t reg_fw_base;
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struct device *generic_dev;
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struct vpu_dev *vdev;
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bool snapshot;
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bool suspend;
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bool hang;
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struct device_attribute core_attr;
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char name[64];
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};
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struct vpu_dev {
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struct device *generic_dev;
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struct v4l2_device v4l2_dev;
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struct video_device *pvpu_encoder_dev;
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struct platform_device *plat_dev;
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struct clk *clk_m0;
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void __iomem *regs_base;
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void __iomem *regs_enc;
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struct mutex dev_mutex;
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struct core_device core_dev[2];
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u_int32 plat_type;
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u_int32 core_num;
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// struct vpu_ctx *ctx[VPU_MAX_NUM_STREAMS];
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};
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struct buffer_addr {
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void *virt_addr;
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dma_addr_t phy_addr;
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u_int32 size;
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};
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enum {
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VPU_ENC_STATUS_INITIALIZED,
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VPU_ENC_STATUS_FORCE_RELEASE = 21,
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VPU_ENC_STATUS_EOS_SEND = 22,
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VPU_ENC_STATUS_START_SEND = 23,
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VPU_ENC_STATUS_START_DONE = 24,
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VPU_ENC_STATUS_STOP_REQ = 25,
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VPU_ENC_STATUS_STOP_SEND = 26,
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VPU_ENC_STATUS_STOP_DONE = 27,
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VPU_ENC_STATUS_CLOSED = 28,
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VPU_ENC_STATUS_CONFIGURED = 29,
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VPU_ENC_STATUS_HANG = 30,
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VPU_ENC_STATUS_KEY_FRAME = 31
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};
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struct vpu_ctx {
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struct vpu_dev *dev;
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struct v4l2_fh fh;
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struct v4l2_ctrl_handler ctrl_handler;
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bool ctrl_inited;
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int str_index;
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unsigned long status;
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struct queue_data q_data[2];
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struct kfifo msg_fifo;
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struct mutex instance_mutex;
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struct work_struct instance_work;
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struct workqueue_struct *instance_wq;
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bool ctx_released;
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struct buffer_addr encoder_stream;
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struct buffer_addr encoder_mem;
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struct buffer_addr encFrame[MEDIAIP_MAX_NUM_WINDSOR_SRC_FRAMES];
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struct buffer_addr refFrame[MEDIAIP_MAX_NUM_WINDSOR_REF_FRAMES];
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struct buffer_addr actFrame;
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struct buffer_addr enc_buffer;
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struct core_device *core_dev;
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struct completion stop_cmp;
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bool power_status;
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};
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#define LVL_DEBUG 4
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#define LVL_INFO 3
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#define LVL_IRQ 2
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#define LVL_ALL 1
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#define LVL_WARN 1
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#define LVL_ERR 0
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#ifndef TAG
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#define TAG "[VPU Encoder]\t "
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#endif
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#define vpu_dbg(level, fmt, arg...) \
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do { \
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if (vpu_dbg_level_encoder >= (level)) \
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pr_info(TAG""fmt, ## arg); \
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} while (0)
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#define vpu_err(fmt, arg...) vpu_dbg(LVL_ERR, fmt, ##arg)
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struct vpu_attr *get_vpu_ctx_attr(struct vpu_ctx *ctx);
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#endif
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