527 lines
15 KiB
C
527 lines
15 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
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* All rights reserved worldwide.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Copyright 2017-2018 NXP
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*
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******************************************************************************
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*
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* API_HDMITX.c
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*
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******************************************************************************
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*/
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#include "API_HDMITX.h"
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#include "util.h"
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#include "opcodes.h"
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#include "mhl_hdtx_top.h"
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#include "source_phy.h"
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#include "address.h"
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#include "source_car.h"
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#include "source_vif.h"
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#include "general_handler.h"
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#include <soc/imx8/soc.h>
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#define B0_SILICON_ID 0x11
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CDN_API_STATUS CDN_API_HDMITX_DDC_READ(state_struct *state,
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HDMITX_TRANS_DATA *data_in,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_macro_command_txrx(state, MB_MODULE_ID_HDMI_TX, HDMI_TX_READ,
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CDN_BUS_TYPE_APB, 3, 1, data_in->slave, 1,
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data_in->offset, 2, data_in->len);
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internal_readmsg(state, 5, 1, &data_out->status, 1, &data_out->slave, 1,
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&data_out->offset, 2, &data_out->len, 0,
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&data_out->buff);
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return CDN_OK;
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}
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CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(state_struct *state,
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HDMITX_TRANS_DATA *data_in,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_block_function(&state->mutex, CDN_API_HDMITX_DDC_READ
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(state, data_in, data_out));
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}
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CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(state_struct *state,
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HDMITX_TRANS_DATA *data_in,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_macro_command_txrx(state, MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE,
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CDN_BUS_TYPE_APB, 4, 1, data_in->slave, 1,
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data_in->offset, 2, data_in->len,
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-data_in->len, data_in->buff);
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internal_readmsg(state, 4, 1, &data_out->status, 1, &data_out->slave, 1,
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&data_out->offset, 2, &data_out->len);
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return CDN_OK;
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}
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CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(state_struct *state,
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HDMITX_TRANS_DATA *data_in,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_block_function(&state->mutex, CDN_API_HDMITX_DDC_WRITE
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(state, data_in, data_out));
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}
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CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(state_struct *state,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_macro_command_txrx(state, MB_MODULE_ID_HDMI_TX,
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HDMI_TX_UPDATE_READ, CDN_BUS_TYPE_APB, 0);
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internal_readmsg(state, 2, 1, &data_out->status, 0, &data_out->buff);
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return CDN_OK;
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}
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CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ_blocking(state_struct *state,
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HDMITX_TRANS_DATA *
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data_out)
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{
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internal_block_function(&state->mutex, CDN_API_HDMITX_DDC_UPDATE_READ
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(state, data_out));
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}
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CDN_API_STATUS CDN_API_HDMITX_READ_EDID(state_struct *state, u8 block,
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u8 segment,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_macro_command_txrx(state, MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID,
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CDN_BUS_TYPE_APB, 2, 1, block, 1, segment);
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internal_readmsg(state, 5, 1, &data_out->status, 1, &data_out->slave, 1,
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&data_out->offset, 2, &data_out->len, 0,
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&data_out->buff);
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return CDN_OK;
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}
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CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(state_struct *state, u8 block,
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u8 segment,
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HDMITX_TRANS_DATA *data_out)
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{
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internal_block_function(&state->mutex, CDN_API_HDMITX_READ_EDID
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(state, block, segment, data_out));
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}
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CDN_API_STATUS
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CDN_API_HDMITX_Set_Mode_blocking(state_struct *state,
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HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
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u32 character_rate)
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{
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CDN_API_STATUS ret;
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GENERAL_Read_Register_response resp;
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HDMITX_TRANS_DATA data_in;
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HDMITX_TRANS_DATA data_out;
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u32 clk_reg_0, clk_reg_1;
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u8 buff = 1;
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/* enable/disable scrambler */
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if (protocol == HDMI_TX_MODE_HDMI_2_0) {
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if (character_rate >= 340000)
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/* enable scrambling + TMDS_Bit_Clock_Ratio */
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buff = 3;
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else
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/* enable scrambling */
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buff = 1;
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} else
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/* disable scrambling */
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buff = 0;
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data_in.buff = &buff;
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data_in.len = 1;
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data_in.slave = 0x54;
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/* TMDS config */
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data_in.offset = 0x20;
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/* Workaround for imx8qm A0 SOC DDC R/W failed issue */
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if (cpu_is_imx8qm() && (imx8_get_soc_revision() < B0_SILICON_ID))
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pr_info("Skip DDC Write for iMX8QM A0 SOC\n");
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else {
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ret = CDN_API_HDMITX_DDC_WRITE_blocking(state, &data_in, &data_out);
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if (ret != CDN_OK)
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pr_warn("CDN_API_HDMITX_DDC_WRITE_blocking ret = %d\n", ret);
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}
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ret = CDN_API_General_Read_Register_blocking(
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state, ADDR_SOURCE_MHL_HD + (HDTX_CONTROLLER << 2), &resp);
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if (ret != CDN_OK)
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return ret;
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/* remove data enable */
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resp.val = resp.val & (~(F_DATA_EN(1)));
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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resp.val);
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if (ret != CDN_OK)
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return ret;
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clk_reg_0 = 0x7c1f;
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clk_reg_1 = 0x7c1f;
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if (protocol == HDMI_TX_MODE_HDMI_2_0) {
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if (character_rate >= 340000) {
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clk_reg_0 = 0;
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clk_reg_1 = 0xFFFFF;
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}
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}
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ret = CDN_API_General_Write_Register_blocking(
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state, ADDR_SOURCE_MHL_HD + (HDTX_CLOCK_REG_0 << 2),
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F_DATA_REGISTER_VAL_0(clk_reg_0));
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if (ret != CDN_OK)
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return ret;
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ret = CDN_API_General_Write_Register_blocking(
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state, ADDR_SOURCE_MHL_HD + (HDTX_CLOCK_REG_1 << 2),
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F_DATA_REGISTER_VAL_1(clk_reg_1));
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if (ret != CDN_OK)
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return ret;
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/* set hdmi mode and preemble mode */
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resp.val = resp.val & (~(F_HDMI_MODE(3)));
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resp.val = resp.val & (~(F_HDMI2_PREAMBLE_EN(1)));
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resp.val =
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(resp.val) | (F_HDMI_MODE(protocol)) | (F_HDMI2_PREAMBLE_EN(1));
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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resp.val);
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if (ret != CDN_OK)
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return ret;
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/* data enable */
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resp.val |= F_DATA_EN(1);
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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resp.val);
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return ret;
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}
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CDN_API_STATUS CDN_API_HDMITX_Init_blocking(state_struct *state)
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{
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CDN_API_STATUS ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCD_PHY +
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(PHY_DATA_SEL << 2),
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F_SOURCE_PHY_MHDP_SEL(1));
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_HPD << 2),
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F_HPD_VALID_WIDTH(4) |
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F_HPD_GLITCH_WIDTH(0));
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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F_HDMI_MODE(1) |
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F_AUTO_MODE(0) | F_GCP_EN(1)
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| F_DATA_EN(1) |
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F_CLEAR_AVMUTE(1) |
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F_HDMI2_PREAMBLE_EN(1) |
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F_HDMI2_CTRL_IL_MODE(1) |
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F_PIC_3D(0XF) |
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F_BCH_EN(1));
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if (ret != CDN_OK)
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return ret;
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/* open CARS */
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_PHY_CAR << 2), 0xF);
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_HDTX_CAR << 2),
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0xFF);
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_PKT_CAR << 2), 0xF);
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_AIF_CAR << 2), 0xF);
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_CIPHER_CAR << 2),
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0xF);
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_CRYPTO_CAR << 2),
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0xF);
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if (ret != CDN_OK)
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return ret;
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_CAR +
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(SOURCE_CEC_CAR << 2), 3);
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if (ret != CDN_OK)
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return ret;
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/* init vif */
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_VIF +
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(HSYNC2VSYNC_POL_CTRL << 2),
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F_HPOL(0) | F_VPOL(0));
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return ret;
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}
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CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(state_struct *state,
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struct drm_display_mode *mode, int bpp,
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VIC_PXL_ENCODING_FORMAT format)
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{
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CDN_API_STATUS ret;
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GENERAL_Read_Register_response resp;
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u32 vsync_lines = mode->vsync_end - mode->vsync_start;
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u32 eof_lines = mode->vsync_start - mode->vdisplay;
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u32 sof_lines = mode->vtotal - mode->vsync_end;
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u32 hblank = mode->htotal - mode->hdisplay;
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u32 hactive = mode->hdisplay;
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u32 vblank = mode->vtotal - mode->vdisplay;
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u32 vactive = mode->vdisplay;
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u32 hfront = mode->hsync_start - mode->hdisplay;
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u32 hback = mode->htotal - mode->hsync_end;
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u32 vfront = eof_lines;
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u32 hsync = hblank - hfront - hback;
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u32 vsync = vsync_lines;
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u32 vback = sof_lines;
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u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) +
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((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2);
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(SCHEDULER_H_SIZE << 2),
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(hactive << 16) + hblank);
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if (ret != CDN_OK)
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return ret;
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(SCHEDULER_V_SIZE << 2),
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(vactive << 16) + vblank);
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if (ret != CDN_OK)
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return ret;
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_SIGNAL_FRONT_WIDTH <<
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2),
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(vfront << 16) + hfront);
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if (ret != CDN_OK)
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return ret;
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_SIGNAL_SYNC_WIDTH <<
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2), (vsync << 16) + hsync);
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if (ret != CDN_OK)
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return ret;
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_SIGNAL_BACK_WIDTH <<
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2), (vback << 16) + hback);
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if (ret != CDN_OK)
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return ret;
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_VIF +
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(HSYNC2VSYNC_POL_CTRL << 2),
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v_h_polarity);
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if (ret != CDN_OK)
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return ret;
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/* Reset Data Enable */
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CDN_API_General_Read_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2), &resp);
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if (ret != CDN_OK)
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return ret;
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/* reset data enable */
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resp.val = resp.val & (~(F_DATA_EN(1)));
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ret = CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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resp.val);
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if (ret != CDN_OK)
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return ret;
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/* set bpp */
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resp.val = resp.val & (~(F_VIF_DATA_WIDTH(3)));
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switch (bpp) {
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case 8:
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resp.val = resp.val | (F_VIF_DATA_WIDTH(0));
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break;
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case 10:
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resp.val = resp.val | (F_VIF_DATA_WIDTH(1));
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break;
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case 12:
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resp.val = resp.val | (F_VIF_DATA_WIDTH(2));
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break;
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case 16:
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resp.val = resp.val | (F_VIF_DATA_WIDTH(3));
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break;
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}
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/* select color encoding */
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resp.val = resp.val & (~(F_HDMI_ENCODING(3)));
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switch (format) {
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case PXL_RGB:
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resp.val = resp.val | (F_HDMI_ENCODING(0));
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break;
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case YCBCR_4_4_4:
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resp.val = resp.val | (F_HDMI_ENCODING(2));
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break;
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case YCBCR_4_2_2:
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resp.val = resp.val | (F_HDMI_ENCODING(1));
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break;
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case YCBCR_4_2_0:
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resp.val = resp.val | (F_HDMI_ENCODING(3));
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break;
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case Y_ONLY:
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/* not exist in hdmi */
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break;
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}
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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resp.val);
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if (ret != CDN_OK)
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return ret;
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/* set data enable */
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resp.val = resp.val | (F_DATA_EN(1));
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ret =
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CDN_API_General_Write_Register_blocking(state, ADDR_SOURCE_MHL_HD +
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(HDTX_CONTROLLER << 2),
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resp.val);
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if (ret != CDN_OK)
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return ret;
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return ret;
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}
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CDN_API_STATUS CDN_API_HDMITX_Disable_GCP(state_struct *state)
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{
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GENERAL_Read_Register_response resp;
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CDN_API_General_Read_Register_blocking(state, ADDR_SOURCE_MHL_HD +(HDTX_CONTROLLER<<2), &resp);
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resp.val = resp.val & (~F_GCP_EN(1));
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return CDN_API_General_Write_Register_blocking(state,
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ADDR_SOURCE_MHL_HD +(HDTX_CONTROLLER<<2), resp.val);
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}
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CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(state_struct *state,
|
|
u8 force, u8 val)
|
|
{
|
|
u32 valToWrite = F_COLOR_DEPTH_VAL(val) | F_COLOR_DEPTH_FORCE(force);
|
|
return CDN_API_General_Write_Register_blocking(state,
|
|
ADDR_SOURCE_MHL_HD +
|
|
(GCP_FORCE_COLOR_DEPTH_CODING
|
|
<< 2), valToWrite);
|
|
|
|
}
|
|
|
|
CDN_API_STATUS CDN_API_HDMITX_ReadEvents(state_struct *state,
|
|
uint32_t *events)
|
|
{
|
|
CDN_API_STATUS ret;
|
|
|
|
if (!state->running) {
|
|
if (!internal_apb_available(state))
|
|
return CDN_BSY;
|
|
|
|
internal_tx_mkfullmsg(state, MB_MODULE_ID_HDMI_TX,
|
|
HDMI_TX_EVENTS, 0);
|
|
state->rxEnable = 1;
|
|
state->bus_type = CDN_BUS_TYPE_APB;
|
|
|
|
return CDN_STARTED;
|
|
}
|
|
|
|
internal_process_messages(state);
|
|
|
|
ret =
|
|
internal_test_rx_head(state, MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS);
|
|
|
|
if (ret != CDN_OK)
|
|
return ret;
|
|
|
|
internal_readmsg(state, 1, 4, events);
|
|
|
|
return CDN_OK;
|
|
}
|
|
|
|
CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(state_struct *state,
|
|
uint32_t *events)
|
|
{
|
|
internal_block_function(&state->mutex, CDN_API_HDMITX_ReadEvents(state, events));
|
|
}
|
|
|
|
CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(state_struct *state, u8 *hpd_sts)
|
|
{
|
|
CDN_API_STATUS ret;
|
|
if (!state->running) {
|
|
if (!internal_apb_available(state))
|
|
return CDN_BSY;
|
|
internal_tx_mkfullmsg(state, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE, 0);
|
|
state->rxEnable = 1;
|
|
state->bus_type = CDN_BUS_TYPE_APB;
|
|
return CDN_STARTED;
|
|
}
|
|
internal_process_messages(state);
|
|
ret =
|
|
internal_test_rx_head(state, MB_MODULE_ID_GENERAL, GENERAL_GET_HPD_STATE);
|
|
if (ret != CDN_OK)
|
|
return ret;
|
|
internal_readmsg(state, 1, 1, hpd_sts);
|
|
return CDN_OK;
|
|
}
|
|
|
|
CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(state_struct *state,
|
|
u8 *hpd_sts)
|
|
{
|
|
internal_block_function(&state->mutex, CDN_API_HDMITX_GetHpdStatus(state, hpd_sts));
|
|
}
|