2e8a5942f8
Actually enabling coherency and adding a CPU on a SMP group are two different operations which can be done separately. This patch splits this in two functions. Moreover as they use common pattern, this patch also creates local low level functions (ll_get_coherency_base and ll_get_cpuid) to be used by the exposed functions (ll_add_cpu_to_smp_group and ll_enable_coherency) Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
109 lines
2.5 KiB
ArmAsm
109 lines
2.5 KiB
ArmAsm
/*
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* Coherency fabric: low level functions
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file implements the assembly function to add a CPU to the
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* coherency fabric. This function is called by each of the secondary
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* CPUs during their early boot in an SMP kernel, this why this
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* function have to callable from assembly. It can also be called by a
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* primary CPU from C code during its boot.
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*/
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#include <linux/linkage.h>
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#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
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#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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.text
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/* Returns with the coherency address in r1 (r0 is untouched)*/
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ENTRY(ll_get_coherency_base)
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mrc p15, 0, r1, c1, c0, 0
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tst r1, #CR_M @ Check MMU bit enabled
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bne 1f
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/* use physical address of the coherency register */
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adr r1, 3f
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ldr r3, [r1]
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ldr r1, [r1, r3]
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b 2f
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1:
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/* use virtual address of the coherency register */
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ldr r1, =coherency_base
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ldr r1, [r1]
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2:
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mov pc, lr
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ENDPROC(ll_get_coherency_base)
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/* Returns with the CPU ID in r3 (r0 is untouched)*/
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ENTRY(ll_get_cpuid)
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mrc 15, 0, r3, cr0, cr0, 5
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and r3, r3, #15
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mov r2, #(1 << 24)
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lsl r3, r2, r3
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ARM_BE8(rev r1, r1)
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mov pc, lr
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ENDPROC(ll_get_cpuid)
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/* ll_add_cpu_to_smp_group, ll_enable_coherency and
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* ll_disable_coherency use strex/ldrex whereas MMU can be off. The
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* Armada XP SoC has an exclusive monitor that can track transactions
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* to Device and/or SO and as such also when MMU is disabled the
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* exclusive transactions will be functional
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*/
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ENTRY(ll_add_cpu_to_smp_group)
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/*
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* r0 being untouched in ll_get_coherency_base and
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* ll_get_cpuid, we can use it to save lr modifing it with the
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* following bl
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*/
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mov r0, lr
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bl ll_get_coherency_base
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bl ll_get_cpuid
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
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1:
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ldrex r2, [r0]
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orr r2, r2, r3
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strex r1, r2, [r0]
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cmp r1, #0
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bne 1b
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mov pc, lr
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ENDPROC(ll_add_cpu_to_smp_group)
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ENTRY(ll_enable_coherency)
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/*
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* r0 being untouched in ll_get_coherency_base and
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* ll_get_cpuid, we can use it to save lr modifing it with the
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* following bl
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*/
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mov r0, lr
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bl ll_get_coherency_base
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bl ll_get_cpuid
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mov lr, r0
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add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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ldrex r2, [r0]
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orr r2, r2, r3
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strex r1, r2, [r0]
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cmp r1, #0
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bne 1b
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dsb
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mov r0, #0
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mov pc, lr
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ENDPROC(ll_enable_coherency)
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.align 2
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3:
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.long coherency_phys_base - .
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