428 lines
13 KiB
Plaintext
428 lines
13 KiB
Plaintext
Freescale i.MX DRM master device
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================================
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The freescale i.MX DRM master device is a virtual device needed to list all
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IPU or other display interface nodes that comprise the graphics subsystem.
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Required properties:
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- compatible: Should be "fsl,imx-display-subsystem"
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- ports: Should contain a list of phandles pointing to display interface ports
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of IPU devices
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example:
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display-subsystem {
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compatible = "fsl,display-subsystem";
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ports = <&ipu_di0>;
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};
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Freescale i.MX IPUv3
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====================
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Required properties:
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- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
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- imx51
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- imx53
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- imx6q
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- imx6qp
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain sync interrupt and error interrupt,
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in this order.
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- resets: phandle pointing to the system reset controller and
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reset line index, see reset/fsl,imx-src.txt for details
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Additional required properties for fsl,imx6qp-ipu:
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- fsl,prg: phandle to prg node associated with this IPU instance
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Optional properties:
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- port@[0-3]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Ports 0 and 1 should correspond to CSI0 and CSI1,
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ports 2 and 3 should correspond to DI0 and DI1, respectively.
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example:
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ipu: ipu@18000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ipu";
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reg = <0x18000000 0x080000000>;
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interrupts = <11 10>;
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resets = <&src 2>;
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ipu_di0: port@2 {
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reg = <2>;
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ipu_di0_disp0: endpoint {
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remote-endpoint = <&display_in>;
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};
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};
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};
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Freescale i.MX PRE (Prefetch Resolve Engine)
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============================================
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Required properties:
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- compatible: should be "fsl,imx6qp-pre"
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- reg: should be register base and length as documented in the
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datasheet
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- clocks : phandle to the PRE axi clock input, as described
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in Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx6q-clock.txt.
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- clock-names: should be "axi"
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- interrupts: should contain the PRE interrupt
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- fsl,iram: phandle pointing to the mmio-sram device node, that should be
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used for the PRE SRAM double buffer.
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example:
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pre@21c8000 {
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compatible = "fsl,imx6qp-pre";
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reg = <0x021c8000 0x1000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks IMX6QDL_CLK_PRE0>;
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clock-names = "axi";
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fsl,iram = <&ocram2>;
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};
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Freescale i.MX PRG (Prefetch Resolve Gasket)
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============================================
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Required properties:
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- compatible: should be "fsl,imx6qp-prg"
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- reg: should be register base and length as documented in the
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datasheet
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- clocks : phandles to the PRG ipg and axi clock inputs, as described
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in Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx6q-clock.txt.
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- clock-names: should be "ipg" and "axi"
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- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
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PRE as the first entry and the muxable PREs following.
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example:
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prg@21cc000 {
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compatible = "fsl,imx6qp-prg";
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reg = <0x021cc000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
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<&clks IMX6QDL_CLK_PRG0_AXI>;
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clock-names = "ipg", "axi";
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fsl,pres = <&pre1>, <&pre2>, <&pre3>;
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Freescale i.MX DPU
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====================
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Required properties:
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- compatible: Should be "fsl,<chip>-dpu"
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- reg: should be register base and length as documented in the
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datasheet
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- intsteer: phandle pointing to interrupt steer.
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- interrupts, interrupt-names: Should contain interrupts and names as
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documented in the datasheet.
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- clocks, clock-names: phandles to the DPU clocks described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The following clocks are expected on i.MX8qm and i.MX8qxp:
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"pll0" - PLL clock for display interface 0
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"pll1" - PLL clock for display interface 1
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"disp0" - pixel clock for display interface 0
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"disp1" - pixel clock for display interface 1
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The needed clock numbers for each are documented in
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Documentation/devicetree/bindings/clock/imx8qm-clock.txt, and in
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Documentation/devicetree/bindings/clock/imx8qxp-clock.txt.
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- power-domains: phandle pointing to power domain.
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- fsl,dpr-channels: phandles to the DPR channels attached to this DPU,
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sorted by memory map addresses. Only valid for i.MX8qm and i.MX8qxp.
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- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU.
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Optional properties:
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- port@[0-1]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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ports 0 and 1 should correspond to display interface 0 and
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display interface 1, respectively.
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example:
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dpu: dpu@56180000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qm-dpu";
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reg = <0x0 0x56180000 0x0 0x40000>;
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intsteer = <&dpu1_intsteer>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_common",
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"irq_stream0a",
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"irq_stream0b",
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"irq_stream1a",
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"irq_stream1b",
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"irq_reserved0",
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"irq_reserved1",
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"irq_blit";
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clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
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<&clk IMX8QM_DC0_PLL1_CLK>,
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<&clk IMX8QM_DC0_DISP0_CLK>,
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<&clk IMX8QM_DC0_DISP1_CLK>;
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clock-names = "pll0", "pll1", "disp0", "disp1";
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power-domains = <&pd_dc0>;
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fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>,
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<&dpr1_channel3>, <&dpr2_channel1>,
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<&dpr2_channel2>, <&dpr2_channel3>;
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fsl,pixel-combiner = <&pixel_combiner1>;
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dpu1_disp1: port@1 {
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reg = <1>;
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dpu1_disp1_lvds0: lvds0-endpoint {
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remote-endpoint = <&ldb1_lvds0>;
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};
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dpu1_disp1_lvds1: lvds1-endpoint {
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remote-endpoint = <&ldb1_lvds1>;
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};
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};
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};
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NXP i.MX Display Controller Subsystem (DCSS)
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=============================================
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Required properties:
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- compatible: Should be "nxp,<chip>-dcss"
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- reg: should be register base and length as documented in the
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datasheet.
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- interrupts, interrupt-names: Should contain interrupts and names as
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documented in the datasheet.
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- interrupt-parent: contains the phandle to IRQ Steer module.
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- clocks, clock-names: phandles to the DCSS clocks described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- disp-dev: can take following values:
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- hdmi_disp: DCSS output goes to HDMI
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- mipi_disp: DCSS output goes to MIPI_DSI
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Optional properties:
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- port@[0-1]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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ports 0 and 1 should correspond to display interface 0 and
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display interface 1, respectively.
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example:
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dcss_drm: dcss@0x32e00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,imx8mq-dcss";
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reg = <0x0 0x32e00000 0x0 0x30000>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>,
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<6 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dpr_dc_ch0", "dpr_dc_ch1", "dpr_dc_ch2", "ctx_ld",
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"dtg_prg1";
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interrupt-parent = <&irqsteer_dcss>;
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clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
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<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
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<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
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<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
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clock-names = "apb", "axi", "rtrm", "pixel", "dtrc";
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assigned-clocks = <&clk IMX8MQ_CLK_DISP_APB_SRC>,
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<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
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<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
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<&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
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<&clk IMX8MQ_CLK_DISP_DTRC_SRC>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
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<&clk IMX8MQ_SYS1_PLL_800M>,
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<&clk IMX8MQ_SYS1_PLL_800M>,
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<&clk IMX8MQ_VIDEO_PLL1_OUT>,
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<&clk IMX8MQ_CLK_25M>;
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assigned-clock-rate = <800000000>, <800000000>, <800000000>, <594000000>, <25000000>;
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disp-dev = "hdmi_disp";
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status = "okay";
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dcss_disp0: port@0 {
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reg = <0>;
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dcss_disp0_imx_stub: imx_stub_conenc {
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remote-endpoint = <&imx_stub_conenc0>;
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};
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};
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};
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NXP i.MX eLCDIF (Enhanced LCD Interface)
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========================================
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Required properties:
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- compatible: should be "fsl,imx8mm-lcdif"
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- reg: should be register base and length as documented in the
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datasheet.
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- interrupts, interrupt-names: Should contain interrupts and names as
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documented in the datasheet.
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- interrupt-parent: contains the phandle to IRQ Steer module.
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- clocks, clock-names: phandles to the LCDIF clocks described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- assigned-clocks, assigned-clock-parents, assigned-clock-rate: configure
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LCDIF related clock sources, clock source parents and clock source rates.
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- lcdif-gpr: a phandle which provides the LCDIF control and gpr registers
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configuration.
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Optional properties:
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- port@0: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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ports 0 should correspond to display interface 0.
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example:
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lcdif: lcdif@32E00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8mm-lcdif";
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reg = <0x0 0x32e00000 0x0 0x10000>;
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clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_DIV>,
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<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MM_CLK_DISP_APB_ROOT>;
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clock-names = "pix", "disp-axi", "disp-apb";
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assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL_SRC>,
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<&clk IMX8MM_CLK_DISP_AXI_SRC>,
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<&clk IMX8MM_CLK_DISP_APB_SRC>;
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assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
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<&clk IMX8MM_SYS_PLL2_1000M>,
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<&clk IMX8MM_SYS_PLL1_800M>;
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assigned-clock-rate = <594000000>, <500000000>, <200000000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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lcdif-gpr = <&dispmix_gpr>;
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status = "disabled";
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lcdif_disp0: port@0 {
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reg = <0>;
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lcdif_to_dsim: endpoint {
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remote-endpoint = <&dsim_from_lcdif>;
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};
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};
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};
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Freescale i.MX8 PC (Pixel Combiner)
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=============================================
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Required properties:
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- compatible: should be "fsl,<chip>-pixel-combiner"
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- reg: should be register base and length as documented in the
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datasheet
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- power-domains: phandle pointing to power domain
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example:
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pixel-combiner@56020000 {
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compatible = "fsl,imx8qm-pixel-combiner";
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reg = <0x0 0x56020000 0x0 0x10000>;
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power-domains = <&pd_dc0>;
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};
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Freescale i.MX8 PRG (Prefetch Resolve Gasket)
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=============================================
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Required properties:
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- compatible: should be "fsl,<chip>-prg"
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- reg: should be register base and length as documented in the
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datasheet
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- clocks: phandles to the PRG apb and rtram clocks, as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt,
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Documentation/devicetree/bindings/clock/imx8qm-clock.txt and
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Documentation/devicetree/bindings/clock/imx8qxp-clock.txt
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- clock-names: should be "apb" and "rtram"
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- power-domains: phandle pointing to power domain
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example:
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prg@56040000 {
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compatible = "fsl,imx8qm-prg";
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reg = <0x0 0x56040000 0x0 0x10000>;
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clocks = <&clk IMX8QM_DC0_PRG0_APB_CLK>,
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<&clk IMX8QM_DC0_PRG0_RTRAM_CLK>;
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clock-names = "apb", "rtram";
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power-domains = <&pd_dc0>;
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};
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Freescale i.MX8 DPRC (Display Prefetch Resolve Channel)
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=======================================================
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Required properties:
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- compatible: should be "fsl,<chip>-dpr-channel"
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- reg: should be register base and length as documented in the
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datasheet
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- fsl,sc-resource: SCU resource number as described in
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Documentation/devicetree/bindings/soc/fsl/imx_rsrc.txt
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- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one
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is the primary PRG and the second one(if available) is the auxiliary PRG
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which is used to fetch luma chunk of a YUV frame with 2 planars.
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- clocks: phandles to the DPRC apb, b and rtram clocks, as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt,
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Documentation/devicetree/bindings/clock/imx8qm-clock.txt and
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Documentation/devicetree/bindings/clock/imx8qxp-clock.txt
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- clock-names: should be "apb", "b" and "rtram"
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- power-domains: phandle pointing to power domain
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example:
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dpr-channel@56100000 {
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compatible = "fsl,imx8qm-dpr-channel";
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reg = <0x0 0x56100000 0x0 0x10000>;
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fsl,sc-resource = <SC_R_DC_0_VIDEO0>;
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fsl,prgs = <&prg4>, <&prg5>;
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clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>,
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<&clk IMX8QM_DC0_DPR1_B_CLK>,
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<&clk IMX8QM_DC0_RTRAM1_CLK>;
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clock-names = "apb", "b", "rtram";
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power-domains = <&pd_dc0>;
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};
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Parallel display support
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========================
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Required properties:
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- compatible: Should be "fsl,imx-parallel-display"
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Optional properties:
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- interface-pix-fmt: How this display is connected to the
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display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
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and "lvds666".
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- edid: verbatim EDID data block describing attached display.
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- ddc: phandle describing the i2c bus handling the display data
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channel
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- port@[0-1]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Port 0 is the input port connected to the IPU display interface,
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port 1 is the output port connected to a panel.
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example:
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display@di0 {
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compatible = "fsl,imx-parallel-display";
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edid = [edid-data];
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interface-pix-fmt = "rgb24";
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port@0 {
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reg = <0>;
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display_in: endpoint {
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remote-endpoint = <&ipu_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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display_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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panel {
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...
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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