cd3db0c4ca
The RMA (RMO is a misnomer) is a concept specific to ppc64 (in fact server ppc64 though I hijack it on embedded ppc64 for similar purposes) and represents the area of memory that can be accessed in real mode (aka with MMU off), or on embedded, from the exception vectors (which is bolted in the TLB) which pretty much boils down to the same thing. We take that out of the generic MEMBLOCK data structure and move it into arch/powerpc where it belongs, renaming it to "RMA" while at it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
253 lines
6.5 KiB
C
253 lines
6.5 KiB
C
/*
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* Modifications by Matt Porter (mporter@mvista.com) to support
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* PPC44x Book E processors.
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*
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* This file contains the routines for initializing the MMU
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* on the 4xx series of chips.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/memblock.h>
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#include <asm/mmu.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include "mmu_decl.h"
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/* Used by the 44x TLB replacement exception handler.
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* Just needed it declared someplace.
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*/
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unsigned int tlb_44x_index; /* = 0 */
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unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
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int icache_44x_need_flush;
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unsigned long tlb_47x_boltmap[1024/8];
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static void __cpuinit ppc44x_update_tlb_hwater(void)
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{
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extern unsigned int tlb_44x_patch_hwater_D[];
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extern unsigned int tlb_44x_patch_hwater_I[];
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/* The TLB miss handlers hard codes the watermark in a cmpli
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* instruction to improve performances rather than loading it
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* from the global variable. Thus, we patch the instructions
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* in the 2 TLB miss handlers when updating the value
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*/
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tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
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tlb_44x_hwater;
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flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
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(unsigned long)&tlb_44x_patch_hwater_D[1]);
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tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
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tlb_44x_hwater;
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flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
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(unsigned long)&tlb_44x_patch_hwater_I[1]);
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}
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/*
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* "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
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*/
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static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
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{
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unsigned int entry = tlb_44x_hwater--;
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ppc44x_update_tlb_hwater();
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mtspr(SPRN_MMUCR, 0);
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__asm__ __volatile__(
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"tlbwe %2,%3,%4\n"
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"tlbwe %1,%3,%5\n"
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"tlbwe %0,%3,%6\n"
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:
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#ifdef CONFIG_PPC47x
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: "r" (PPC47x_TLB2_S_RWX),
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#else
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: "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
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#endif
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"r" (phys),
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"r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
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"r" (entry),
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"i" (PPC44x_TLB_PAGEID),
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"i" (PPC44x_TLB_XLAT),
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"i" (PPC44x_TLB_ATTRIB));
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}
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static int __init ppc47x_find_free_bolted(void)
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{
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unsigned int mmube0 = mfspr(SPRN_MMUBE0);
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unsigned int mmube1 = mfspr(SPRN_MMUBE1);
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if (!(mmube0 & MMUBE0_VBE0))
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return 0;
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if (!(mmube0 & MMUBE0_VBE1))
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return 1;
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if (!(mmube0 & MMUBE0_VBE2))
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return 2;
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if (!(mmube1 & MMUBE1_VBE3))
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return 3;
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if (!(mmube1 & MMUBE1_VBE4))
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return 4;
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if (!(mmube1 & MMUBE1_VBE5))
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return 5;
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return -1;
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}
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static void __init ppc47x_update_boltmap(void)
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{
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unsigned int mmube0 = mfspr(SPRN_MMUBE0);
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unsigned int mmube1 = mfspr(SPRN_MMUBE1);
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if (mmube0 & MMUBE0_VBE0)
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__set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
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tlb_47x_boltmap);
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if (mmube0 & MMUBE0_VBE1)
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__set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
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tlb_47x_boltmap);
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if (mmube0 & MMUBE0_VBE2)
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__set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
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tlb_47x_boltmap);
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if (mmube1 & MMUBE1_VBE3)
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__set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
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tlb_47x_boltmap);
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if (mmube1 & MMUBE1_VBE4)
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__set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
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tlb_47x_boltmap);
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if (mmube1 & MMUBE1_VBE5)
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__set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
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tlb_47x_boltmap);
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}
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/*
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* "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
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*/
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static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
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{
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unsigned int rA;
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int bolted;
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/* Base rA is HW way select, way 0, bolted bit set */
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rA = 0x88000000;
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/* Look for a bolted entry slot */
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bolted = ppc47x_find_free_bolted();
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BUG_ON(bolted < 0);
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/* Insert bolted slot number */
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rA |= bolted << 24;
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pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
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virt, phys, bolted);
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mtspr(SPRN_MMUCR, 0);
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__asm__ __volatile__(
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"tlbwe %2,%3,0\n"
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"tlbwe %1,%3,1\n"
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"tlbwe %0,%3,2\n"
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:
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: "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
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PPC47x_TLB2_SX
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#ifdef CONFIG_SMP
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| PPC47x_TLB2_M
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#endif
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),
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"r" (phys),
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"r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
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"r" (rA));
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}
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void __init MMU_init_hw(void)
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{
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/* This is not useful on 47x but won't hurt either */
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ppc44x_update_tlb_hwater();
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flush_instruction_cache();
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}
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unsigned long __init mmu_mapin_ram(unsigned long top)
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{
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unsigned long addr;
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/* Pin in enough TLBs to cover any lowmem not covered by the
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* initial 256M mapping established in head_44x.S */
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for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
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addr += PPC_PIN_SIZE) {
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if (mmu_has_feature(MMU_FTR_TYPE_47x))
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ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
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else
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ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
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}
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if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
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ppc47x_update_boltmap();
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#ifdef DEBUG
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{
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int i;
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printk(KERN_DEBUG "bolted entries: ");
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for (i = 0; i < 255; i++) {
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if (test_bit(i, tlb_47x_boltmap))
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printk("%d ", i);
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}
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printk("\n");
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}
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#endif /* DEBUG */
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}
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return total_lowmem;
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}
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void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/* We don't currently support the first MEMBLOCK not mapping 0
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* physical on those processors
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*/
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BUG_ON(first_memblock_base != 0);
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/* 44x has a 256M TLB entry pinned at boot */
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memblock_set_current_limit(min_t(u64, first_memblock_size, PPC_PIN_SIZE));
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}
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#ifdef CONFIG_SMP
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void __cpuinit mmu_init_secondary(int cpu)
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{
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unsigned long addr;
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/* Pin in enough TLBs to cover any lowmem not covered by the
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* initial 256M mapping established in head_44x.S
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*
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* WARNING: This is called with only the first 256M of the
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* linear mapping in the TLB and we can't take faults yet
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* so beware of what this code uses. It runs off a temporary
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* stack. current (r2) isn't initialized, smp_processor_id()
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* will not work, current thread info isn't accessible, ...
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*/
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for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
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addr += PPC_PIN_SIZE) {
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if (mmu_has_feature(MMU_FTR_TYPE_47x))
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ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
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else
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ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
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}
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}
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#endif /* CONFIG_SMP */
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