6e89e831a9
More than one kernel developer has expressed the opinion that the LKMM should enforce ordering of writes by locking. In other words, given the following code: WRITE_ONCE(x, 1); spin_unlock(&s): spin_lock(&s); WRITE_ONCE(y, 1); the stores to x and y should be propagated in order to all other CPUs, even though those other CPUs might not access the lock s. In terms of the memory model, this means expanding the cumul-fence relation. Locks should also provide read-read (and read-write) ordering in a similar way. Given: READ_ONCE(x); spin_unlock(&s); spin_lock(&s); READ_ONCE(y); // or WRITE_ONCE(y, 1); the load of x should be executed before the load of (or store to) y. The LKMM already provides this ordering, but it provides it even in the case where the two accesses are separated by a release/acquire pair of fences rather than unlock/lock. This would prevent architectures from using weakly ordered implementations of release and acquire, which seems like an unnecessary restriction. The patch therefore removes the ordering requirement from the LKMM for that case. There are several arguments both for and against this change. Let us refer to these enhanced ordering properties by saying that the LKMM would require locks to be RCtso (a bit of a misnomer, but analogous to RCpc and RCsc) and it would require ordinary acquire/release only to be RCpc. (Note: In the following, the phrase "all supported architectures" is meant not to include RISC-V. Although RISC-V is indeed supported by the kernel, the implementation is still somewhat in a state of flux and therefore statements about it would be premature.) Pros: The kernel already provides RCtso ordering for locks on all supported architectures, even though this is not stated explicitly anywhere. Therefore the LKMM should formalize it. In theory, guaranteeing RCtso ordering would reduce the need for additional barrier-like constructs meant to increase the ordering strength of locks. Will Deacon and Peter Zijlstra are strongly in favor of formalizing the RCtso requirement. Linus Torvalds and Will would like to go even further, requiring locks to have RCsc behavior (ordering preceding writes against later reads), but they recognize that this would incur a noticeable performance degradation on the POWER architecture. Linus also points out that people have made the mistake, in the past, of assuming that locking has stronger ordering properties than is currently guaranteed, and this change would reduce the likelihood of such mistakes. Not requiring ordinary acquire/release to be any stronger than RCpc may prove advantageous for future architectures, allowing them to implement smp_load_acquire() and smp_store_release() with more efficient machine instructions than would be possible if the operations had to be RCtso. Will and Linus approve this rationale, hypothetical though it is at the moment (it may end up affecting the RISC-V implementation). The same argument may or may not apply to RMW-acquire/release; see also the second Con entry below. Linus feels that locks should be easy for people to use without worrying about memory consistency issues, since they are so pervasive in the kernel, whereas acquire/release is much more of an "experts only" tool. Requiring locks to be RCtso is a step in this direction. Cons: Andrea Parri and Luc Maranget think that locks should have the same ordering properties as ordinary acquire/release (indeed, Luc points out that the names "acquire" and "release" derive from the usage of locks). Andrea points out that having different ordering properties for different forms of acquires and releases is not only unnecessary, it would also be confusing and unmaintainable. Locks are constructed from lower-level primitives, typically RMW-acquire (for locking) and ordinary release (for unlock). It is illogical to require stronger ordering properties from the high-level operations than from the low-level operations they comprise. Thus, this change would make while (cmpxchg_acquire(&s, 0, 1) != 0) cpu_relax(); an incorrect implementation of spin_lock(&s) as far as the LKMM is concerned. In theory this weakness can be ameliorated by changing the LKMM even further, requiring RMW-acquire/release also to be RCtso (which it already is on all supported architectures). As far as I know, nobody has singled out any examples of code in the kernel that actually relies on locks being RCtso. (People mumble about RCU and the scheduler, but nobody has pointed to any actual code. If there are any real cases, their number is likely quite small.) If RCtso ordering is not needed, why require it? A handful of locking constructs (qspinlocks, qrwlocks, and mcs_spinlocks) are built on top of smp_cond_load_acquire() instead of an RMW-acquire instruction. It currently provides only the ordinary acquire semantics, not the stronger ordering this patch would require of locks. In theory this could be ameliorated by requiring smp_cond_load_acquire() in combination with ordinary release also to be RCtso (which is currently true on all supported architectures). On future weakly ordered architectures, people may be able to implement locks in a non-RCtso fashion with significant performance improvement. Meeting the RCtso requirement would necessarily add run-time overhead. Overall, the technical aspects of these arguments seem relatively minor, and it appears mostly to boil down to a matter of opinion. Since the opinions of senior kernel maintainers such as Linus, Peter, and Will carry more weight than those of Luc and Andrea, this patch changes the model in accordance with the maintainers' wishes. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Andrea Parri <andrea.parri@amarulasolutions.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: akiyks@gmail.com Cc: boqun.feng@gmail.com Cc: dhowells@redhat.com Cc: j.alglave@ucl.ac.uk Cc: linux-arch@vger.kernel.org Cc: luc.maranget@inria.fr Cc: npiggin@gmail.com Cc: parri.andrea@gmail.com Link: http://lkml.kernel.org/r/20180926182920.27644-2-paulmck@linux.ibm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
129 lines
3.8 KiB
Plaintext
129 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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(*
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* Copyright (C) 2015 Jade Alglave <j.alglave@ucl.ac.uk>,
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* Copyright (C) 2016 Luc Maranget <luc.maranget@inria.fr> for Inria
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* Copyright (C) 2017 Alan Stern <stern@rowland.harvard.edu>,
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* Andrea Parri <parri.andrea@gmail.com>
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*
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* An earlier version of this file appeared in the companion webpage for
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* "Frightening small children and disconcerting grown-ups: Concurrency
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* in the Linux kernel" by Alglave, Maranget, McKenney, Parri, and Stern,
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* which appeared in ASPLOS 2018.
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*)
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"Linux-kernel memory consistency model"
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(*
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* File "lock.cat" handles locks and is experimental.
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* It can be replaced by include "cos.cat" for tests that do not use locks.
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*)
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include "lock.cat"
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(*******************)
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(* Basic relations *)
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(*******************)
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(* Fences *)
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let rmb = [R \ Noreturn] ; fencerel(Rmb) ; [R \ Noreturn]
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let wmb = [W] ; fencerel(Wmb) ; [W]
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let mb = ([M] ; fencerel(Mb) ; [M]) |
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([M] ; fencerel(Before-atomic) ; [RMW] ; po? ; [M]) |
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([M] ; po? ; [RMW] ; fencerel(After-atomic) ; [M]) |
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([M] ; po? ; [LKW] ; fencerel(After-spinlock) ; [M])
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let gp = po ; [Sync-rcu] ; po?
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let strong-fence = mb | gp
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(* Release Acquire *)
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let acq-po = [Acquire] ; po ; [M]
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let po-rel = [M] ; po ; [Release]
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let po-unlock-rf-lock-po = po ; [UL] ; rf ; [LKR] ; po
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(**********************************)
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(* Fundamental coherence ordering *)
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(**********************************)
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(* Sequential Consistency Per Variable *)
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let com = rf | co | fr
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acyclic po-loc | com as coherence
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(* Atomic Read-Modify-Write *)
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empty rmw & (fre ; coe) as atomic
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(**********************************)
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(* Instruction execution ordering *)
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(**********************************)
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(* Preserved Program Order *)
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let dep = addr | data
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let rwdep = (dep | ctrl) ; [W]
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let overwrite = co | fr
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let to-w = rwdep | (overwrite & int)
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let to-r = addr | (dep ; rfi)
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let fence = strong-fence | wmb | po-rel | rmb | acq-po
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let ppo = to-r | to-w | fence | (po-unlock-rf-lock-po & int)
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(* Propagation: Ordering from release operations and strong fences. *)
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let A-cumul(r) = rfe? ; r
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let cumul-fence = A-cumul(strong-fence | po-rel) | wmb | po-unlock-rf-lock-po
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let prop = (overwrite & ext)? ; cumul-fence* ; rfe?
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(*
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* Happens Before: Ordering from the passage of time.
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* No fences needed here for prop because relation confined to one process.
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*)
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let hb = ppo | rfe | ((prop \ id) & int)
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acyclic hb as happens-before
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(****************************************)
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(* Write and fence propagation ordering *)
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(****************************************)
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(* Propagation: Each non-rf link needs a strong fence. *)
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let pb = prop ; strong-fence ; hb*
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acyclic pb as propagation
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(*******)
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(* RCU *)
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(*******)
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(*
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* Effect of read-side critical section proceeds from the rcu_read_lock()
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* onward on the one hand and from the rcu_read_unlock() backwards on the
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* other hand.
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*)
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let rscs = po ; crit^-1 ; po?
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(*
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* The synchronize_rcu() strong fence is special in that it can order not
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* one but two non-rf relations, but only in conjunction with an RCU
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* read-side critical section.
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*)
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let rcu-link = hb* ; pb* ; prop
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(*
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* Any sequence containing at least as many grace periods as RCU read-side
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* critical sections (joined by rcu-link) acts as a generalized strong fence.
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*)
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let rec rcu-fence = gp |
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(gp ; rcu-link ; rscs) |
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(rscs ; rcu-link ; gp) |
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(gp ; rcu-link ; rcu-fence ; rcu-link ; rscs) |
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(rscs ; rcu-link ; rcu-fence ; rcu-link ; gp) |
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(rcu-fence ; rcu-link ; rcu-fence)
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(* rb orders instructions just as pb does *)
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let rb = prop ; rcu-fence ; hb* ; pb*
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irreflexive rb as rcu
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(*
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* The happens-before, propagation, and rcu constraints are all
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* expressions of temporal ordering. They could be replaced by
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* a single constraint on an "executes-before" relation, xb:
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*
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* let xb = hb | pb | rb
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* acyclic xb as executes-before
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*)
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